Shift Register Bootstrapped Set Node for OLED Scan Pulse Stability
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Solution Overview
Problem
Conventional shift registers in organic light emitting diode (OLED) display devices face challenges in stably outputting scan pulses with composite waveforms due to deviations in driving currents, requiring larger transistors which increase device size, and struggle with low voltage clock pulses.
Innovation Solution
A shift register design that uses a bootstrapped set node with a floating structure, allowing for stable output of composite scan pulses (A-scan and B-scan pulses) even with low voltage clock pulses, achieved through a configuration of stages with A-sub-stages, B-sub-stages, and a scan output controller that generates and controls A-scan and B-scan pulses based on external control signals and clock pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sizes of output transistors are increased to stably output scan pulses, then the stability of scan pulse output is improved, but the area of the display device increases
Solution Approach 1:
The shift register is divided into multiple stages (first stage, second stage, third stage) with each stage containing A-sub-stages and B-sub-stages. This segmentation allows the complex scan pulse generation function to be distributed across smaller units, enabling stable output without requiring large transistors in a single location.
Solution Approach 2:
The patent implements a nested structure where A-sub-stages and B-sub-stages are contained within each stage, and stages are connected in sequence. The A-set nodes and B-set nodes are connected through floating diffusion regions, creating a nested architecture that maintains signal stability while reducing the size of individual switching components.
2Device complexity
If a multiplexer structure is used to generate composite waveforms, then the complexity of waveform generation is reduced, but the voltage stability at set nodes deteriorates
Solution Approach 1:
The patent employs feedback mechanisms where the output of each stage is fed back to control the next stage. The A-carry pulse and B-carry pulse are generated based on the state of A-set nodes and B-set nodes respectively, and these carry pulses control subsequent stages. This feedback ensures voltage stability at set nodes while maintaining waveform generation complexity at acceptable levels.
Solution Approach 2:
The patent introduces floating diffusion regions as intermediaries between A-set nodes and B-set nodes. These floating diffusion regions act as mediators that couple the A-sub-stages and B-sub-stages without direct connection, allowing voltage stabilization while maintaining the multiplexer-like waveform generation capability.
3Ease of manufacture
If fixed constant voltage is used externally, then the simplicity of voltage supply is improved, but the adaptability to low voltage clock pulses deteriorates
Solution Approach 1:
The patent transitions from static fixed voltage to dynamic voltage control. The VSET node voltage is dynamically adjusted based on the clock pulse signals received. When clock pulses are low voltage, the floating diffusion region and feedback mechanisms automatically adjust the set node voltage to maintain proper operation. This dynamic adaptation allows the system to work with varying voltage conditions while maintaining ease of external voltage supply.
Data Source
AI summary
A shift register includes a plurality of stages each for outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes k A-sub-stages each for controlling a voltage at an A-set node and a voltage at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.