Shift Register with Bootstrapped Set Node for Stable Scan Pulse Output
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional shift registers in OLED displays face challenges in stably outputting scan pulses with composite waveforms due to deviations in driving currents, requiring larger transistors which increase device size, and struggle with outputting scan pulses using low voltage clock pulses.
Innovation Solution
A shift register design that uses a bootstrapped set node and floating structure, generating A-scan and B-scan pulses with k composite pulses, where at least one stage includes A-sub and B-sub stages for controlling voltages and generating carry pulses based on external control signals and clock pulses, allowing for stable output even with low voltage clock pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiplexer structure is used to output scan pulses with larger transistor sizes, then the stability of scan pulse output is improved, but the device size increases
Solution Approach 1:
The shift register stage is divided into A-sub-stage and B-sub-stage, each handling different scan pulses (A-scan and B-scan). This segmentation allows independent optimization of each sub-stage's transistor size, reducing the overall device area while maintaining stable output through distributed functionality
Solution Approach 2:
The patent changes the voltage parameter at the set node from a fixed external voltage to a dynamically bootstrapped voltage that rises to match the clock pulse voltage. This parameter change enables smaller transistors to achieve the same driving capability, reducing device area while maintaining output stability
2Reliability
If larger transistor sizes are used to switch scan pulses, then the stability of scan pulse output is improved, but the transistor size and device area increase
Solution Approach 1:
The set node is pre-charged to a high voltage level before the clock pulse arrives. This preliminary action ensures that when the clock pulse switches the scan pulse, the transistor operates with optimal voltage differential, achieving stable output with smaller transistor sizes
Solution Approach 2:
The set node acts as an intermediary element that bootstraps to the clock pulse voltage level. This intermediary mechanism transfers the high voltage from the clock pulse to control the scan output, enabling smaller transistors to switch the scan pulses effectively without compromising stability
3Device complexity
If fixed constant voltage is used externally, then the circuit structure is simple, but the scan pulse output becomes unstable when clock pulses have low voltage
Solution Approach 1:
The set node voltage transitions from a static fixed voltage to a dynamic voltage that automatically adjusts and bootstraps to match the clock pulse voltage level. This dynamic adaptation ensures stable scan pulse output regardless of the clock pulse voltage level, while adding minimal circuit complexity through the bootstrapping mechanism
Data Source
AI summary
A shift register includes a plurality of stages each outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node. The voltage at the at least one A-reset node and any one A-clock pulse, at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.