Shift Register Unit Capacitor Control for Display Gate Driving
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Solution Overview
Problem
Existing shift register units in display devices require a large number of transistors and complex connections, leading to increased process difficulty and manufacturing cost, especially when achieving signal output with multiple control signals.
Innovation Solution
A shift register unit comprising an input circuit, control circuit, reset circuit, output circuit, and capacitors, where the first capacitor is coupled between the clock signal terminal and the second node, allowing the level of the second node to be controlled in the reset-maintaining phase, simplifying the structure and reducing the need for multiple transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple transistors and complex connections are used to achieve signal output with multiple control signals, then the signal output control capability is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The first capacitor is designed to perform multiple functions: it maintains the voltage level of the second node during the reset-maintaining phase, and also controls the output signal during the output phase. This multi-functional design eliminates the need for separate control transistors, reducing device complexity while maintaining full signal output control capability across all operating phases.
Solution Approach 2:
The first capacitor utilizes the voltage difference between the clock signal terminal and the second node to automatically control the output signal without requiring external transistor control. The capacitor's inherent electrical properties (voltage storage and release) are leveraged to perform the control function that would otherwise require active transistor management, thereby simplifying the circuit structure.
2Manufacturing precision
If multiple transistors are used to control signal levels, then the signal control precision is improved, but the process difficulty and manufacturing cost increase
Solution Approach 1:
The invention extracts the control function from the transistor domain and relocates it to the capacitor domain. By removing the need for control transistors and replacing their function with the first capacitor's voltage storage and release characteristics, the patent reduces the number of transistor components while maintaining precise signal level control through the capacitor's inherent electrical behavior.
3Device complexity
If a simple capacitor-based control is used for the second node, then the device complexity is reduced, but the reliability at high temperatures may be affected
Solution Approach 1:
The first capacitor is configured to maintain the voltage level of the second node during the reset-maintaining phase before the output phase begins. This pre-maintenance of voltage level compensates for potential high-temperature effects during subsequent operation, ensuring stable transistor threshold voltages and reliable signal output even under thermal stress conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables stable signal output and prolongs the service life of the shift register unit, particularly at high temperatures, by controlling the second node using a single capacitor, thereby reducing process complexity and manufacturing costs.
Implementation Method 1
a first capacitor coupled between the clock signal terminal and the second node
Data Source
AI summary
A shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a control circuit, a reset circuit, an output circuit and a first capacitor, where the input circuit provides a signal from an input signal terminal to a first node; the control circuit controls signals from the first node and a second node; the reset circuit provides a signal from a reference signal terminal to the first node; the output circuit provides a signal from a clock signal terminal to a signal output terminal, and provides the signal from the reference signal terminal to the signal output terminal; and the first capacitor is coupled between the clock signal terminal and the second node.