Shift Register Capacitor Stabilization for Display Driver Stability

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Solution Overview

Problem

Existing shift registers in display screens are unstable due to potential contention issues when a low-level signal is not timely written into a node, leading to abnormal output and instability in gate driver circuits.

Innovation Solution

A shift register design incorporating multiple modules, including input, control, and coupling modules with capacitors to stabilize electric potentials, allowing for flexible shifting of high/low-level trigger signals and operation as either a scan or light-emission driver circuit, with clock signals rewritten at half-cycle intervals to maintain stable output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a traditional 5T2C shift register structure is used, then the device complexity is reduced, but the output stability deteriorates due to contention issues when low-level signals are not timely written

Engineering Contradiction:
Improveshift register structureVSAvoidoutput stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The shift register is divided into multiple independent control modules (first control module, second control module, third control module) with distinct functions. Each module manages specific nodes (first node, second node, third node, fourth node) separately, allowing independent control of signal writing and potential contention prevention through coordinated timing of control signals.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Capacitors are pre-connected to various nodes (first capacitor to second node, second capacitor to first node, third capacitor to third node, fourth capacitor to fourth node) to maintain electric potentials before signals are written. This preliminary setup ensures that nodes have stable reference potentials, preventing abnormal outputs even when signal writing is delayed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If multiple control modules and capacitors are added to improve output stability, then the reliability is improved, but the device complexity increases

Engineering Contradiction:
Improveoutput stabilityVSAvoidshift register structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The control modules serve multiple functions: the first control module manages signal transmission to the first node, the second control module handles both first node and second clock signal, the third control module manages third node and reference signal transmission. This multi-functionality reduces the need for separate dedicated components for each function, balancing reliability improvement with complexity management.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple capacitors are strategically combined with control modules to serve dual purposes: the second capacitor connects to both the first node and the second control module, allowing it to stabilize the first node while working in conjunction with the control module's signal management functions.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If clock signals are rewritten at half-cycle intervals, then the adaptability to different driver modes is improved, but the control complexity increases

Engineering Contradiction:
Improvedriver mode flexibilityVSAvoidcontrol signal timing
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Clock signals are rewritten at regular half-cycle intervals in a periodic manner. The first clock signal terminal and second clock signal terminal alternately update their signals at these intervals, creating a rhythmic control pattern that simplifies timing coordination while enabling the circuit to adapt to different operating modes through phase adjustments.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed shift register design ensures stable output waveforms and operation across various driver modes, even with significant threshold drifting, by using capacitors to maintain node potentials and provide a larger process window.

Implementation Method 1

the first coupling module includes a first capacitor electrically connected with the second node, and configured to stable the electric potential of the second node; the second coupling module includes a second capacitor electrically connected with the first node and the second control module, and configured to stabilize the electric potential of the first node; the third coupling module includes a third capacitor electrically connected with the third node and the first reference signal terminal, and configured to stabilize the electric potential of the third node; and the fourth coupling module includes a fourth capacitor electrically connected with the fourth node and the second reference signal terminal, and configured to stabilize the electric potential of the fourth node

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10403195B2Shift register, method for driving the same, and display device
Publication Date: 2019.09.03 WUHAN TIANMA MICRO ELECTRONICS CO LTD
  • US10403195B2 patent drawing
  • US10403195B2 patent drawing
  • US10403195B2 patent drawing

AI summary

Embodiments of the disclosure provide a shift register, a method for driving the same, and a display device, and the shift register includes: a first input module and a second input module, connected respectively with an input signal terminal and a first clock signal terminal; a first control module and a second control module connected with a second clock signal terminal; a third control module connected with a first reference signal terminal; and an output module and a plurality of capacitors, connected respectively with the first reference signal terminal, the second reference signal terminal, and the output signal terminal.