Shift Register Eliminates Storage Capacitor for Narrow Bezel Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate drivers in liquid crystal displays require storage capacitors, which occupy large areas and hinder the implementation of narrow-bezel designs due to their size constraints.
Innovation Solution
A shift register design that eliminates the need for storage capacitors by incorporating a NOR gate circuit, a latch circuit, and an output control circuit, allowing for a simpler structure and reduced area usage, facilitating narrow-bezel displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a storage capacitor is disposed in the shift register to maintain output voltage, then the output voltage stability is improved, but the area of the shift register increases
Solution Approach 1:
The patent extracts and eliminates the storage capacitor from the shift register circuit by redesigning it as a push-pull inverter structure. This removal of the unnecessary component directly reduces the circuit area while the push-pull configuration inherently maintains output voltage stability through its complementary transistor design that actively drives both high and low states.
Solution Approach 2:
The patent changes the operational parameters of the shift register by transitioning from a latched configuration requiring capacitor storage to a dynamic push-pull inverter configuration. This parameter change enables the circuit to maintain output stability through active driving rather than passive storage, thereby reducing area requirements.
2Reliability
If a conventional shift register with storage capacitor is used, then the output voltage can be maintained, but the structure becomes complex
Solution Approach 1:
The patent extracts and removes the storage capacitor and associated latching circuitry from the shift register. This extraction simplifies the overall structure by eliminating redundant components while the push-pull inverter design inherently provides the necessary output maintenance functionality through its complementary transistor architecture.
Solution Approach 2:
The patent merges the functions of voltage storage and output driving into a single push-pull inverter structure. The complementary transistors work together to both maintain output voltage and drive the signal, combining multiple functions into one integrated circuit block that is simpler than the conventional separated capacitor and latch structure.
3Reliability
If storage capacitors are included in each shift register stage, then the signal can be latched, but the overall display area increases
Solution Approach 1:
The patent extracts and eliminates the storage capacitor from each shift register stage, replacing the latching function with a dynamic push-pull inverter design. This removal directly reduces the area consumed by each stage, enabling narrower bezels and more compact display configurations while maintaining signal integrity through active driving.
Solution Approach 2:
The patent transitions from a static latched configuration requiring capacitors to a dynamic push-pull inverter configuration that actively maintains signals through continuous complementary transistor operation. This dynamic approach eliminates the need for large capacitor structures while maintaining signal latching functionality through regulated voltage switching.
Data Source
AI summary
The present invention provides a shift register and a method for driving the same, a gate driving circuit and a display device, the shift register includes a NOR gate circuit, a latch circuit and an output control circuit. First to fourth input terminals of the NOR gate circuit are connected to a clock control signal terminal, a signal input terminal, a high-level power supply terminal and a low-level power supply terminal, respectively, and an output terminal thereof is connected to a first input terminal of the latch circuit; second to fourth input terminals of the latch circuit are connected to the signal input terminal, the high-level power supply terminal and the low-level power supply terminal, respectively, and first and second output terminals thereof are both connected to the output control circuit, which is connected to the clock control signal terminal, the low-level power supply terminal and a signal output terminal.