Shift Register Capacitor Noise Compensation
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Solution Overview
Problem
The output of shift registers in display devices is unstable due to threshold voltage drift of transistors over time, leading to noise and abnormal display issues.
Innovation Solution
A shift register design that includes an input circuit, a reset circuit, a control circuit, and output circuits with capacitors to stabilize the signal output, compensating for load capacitance and reducing noise by combining the charging and discharging processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional shift register is used in display devices, then the device can operate with basic functionality, but the output signal becomes unstable over time due to threshold voltage drift of transistors
Solution Approach 1:
The patent applies preliminary action by pre-charging the output node through a dedicated charging transistor before the main switching operation. This pre-charging action compensates for the threshold voltage drop that will occur during signal transmission, ensuring that the output signal maintains its intended voltage level even after transistor threshold drift occurs during operation.
Solution Approach 2:
The patent changes the voltage parameters dynamically by introducing separate charging and discharging paths with different voltage levels. The output node is charged to a higher voltage level than the standard logic level, and this elevated voltage compensates for the threshold voltage drift of subsequent transistors in the signal chain, maintaining signal integrity over extended operation periods.
2Productivity
If transistors are used in shift register outputs, then signal transmission is enabled, but threshold voltage drift causes noise and abnormal display issues over time
Solution Approach 1:
The patent implements beforehand cushioning by creating a voltage buffer through the charging transistor that compensates for upcoming threshold voltage drops. This cushioning voltage reserve prevents the signal from degrading into noise during transmission through subsequent transistors, thereby preventing abnormal display issues before they occur.
Solution Approach 2:
The patent introduces an intermediary charging transistor that acts as a buffer between the signal source and the output node. This intermediary component isolates the main signal path from the effects of threshold voltage drift, allowing signal transmission to proceed without the harmful noise generation that would otherwise occur.
3Reliability
If the output node capacitance is increased to stabilize signals, then signal stability improves, but the charging and discharging time increases
Solution Approach 1:
The patent applies dynamics by making the capacitance effective value variable through selective transistor switching. During charging phases, the charging transistor is activated to quickly charge the output node capacitance. During discharge phases, the charging transistor is turned off and the discharging path is activated. This dynamic control allows the system to optimize between charging speed and signal stability at different operational moments.
Solution Approach 2:
The patent implements periodic action through alternating charging and discharging cycles controlled by the charging transistor. The transistor is periodically activated to charge the output node when signal stability is needed, and periodically deactivated to allow rapid discharge when speed is prioritized. This periodic switching creates an optimized balance between signal stability and response time throughout the operational cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves signal stability and reduces noise in shift register outputs, enhancing the reliability of display devices by maintaining signal integrity over time.
Implementation Method 1
a first capacitor C1, having a first terminal electrically connected to the cascade signal output terminal COUT and a second terminal electrically connected to a fixed voltage signal terminal GS
Implementation Method 2
compensating for load capacitance and reducing noise by combining the charging and discharging processes
Data Source
AI summary
Provided are a shift register and a driving method thereof, a drive circuit and a display device. A first capacitor is provided with a first terminal electrically connected to a cascade signal output terminal and a second terminal electrically connected to a fixed voltage signal terminal, so that a load capacitance of the cascade signal output terminal is compensated, and the charging and discharging process of the first capacitor is combined to reduce a noise of a signal of the cascade signal output terminal and improve the signal stability of the cascade signal output terminal.