Shift Register Circuit with Isolated Carry Signal Output
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Solution Overview
Problem
In image display apparatuses, existing shift register circuits used as gate line driving circuits face signal delay issues due to the load on gate lines, which affects the operation speed and display quality, especially when connected in cascade.
Innovation Solution
A shift register circuit design that includes separate output terminals for gate line driving signals and carry signals, with individual transistors and driving circuits for each, ensuring that delays in one signal do not influence the other, allowing for faster operation by maintaining the speed of the carry signal despite potential delays in the gate line driving signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If an output terminal drives both gate line and succeeding-stage unit shift register, then device complexity is reduced, but signal delay increases due to load influence
Solution Approach 1:
The patent divides the single output terminal into two separate output terminals: one dedicated to driving the gate line and another dedicated to driving the succeeding-stage unit shift register. This segmentation isolates the load influences, allowing each terminal to drive its respective load without interference, thereby resolving the signal delay problem while maintaining manageable device complexity through modular design.
2Device complexity
If gate line driving signal and carry signal share common control nodes, then device complexity is reduced, but carry signal speed is influenced by gate line driving signal variations
Solution Approach 1:
The patent separates the control nodes for the gate line driving signal and carry signal into distinct nodes. The gate line driving signal is controlled by a first control node while the carry signal is controlled by a second control node. This segmentation prevents variations in the gate line driving signal from directly influencing the carry signal speed, thereby improving signal speed stability and reliability while maintaining reasonable control circuit complexity.
3Speed
If rise time of gate line driving signal decreases due to temperature or threshold voltage variations, then operation speed is reduced, but separate transistor control adds device complexity
Solution Approach 1:
The patent employs separate control circuits for the gate line driving transistor and the carry signal transistor. The gate line driving transistor is controlled by a first control circuit that responds to the gate line driving signal, while the carry signal transistor is controlled by a second control circuit that responds to the carry signal. This segmentation allows independent optimization of each signal path, enabling faster rise times for both signals without requiring complex interdependent control mechanisms, thus improving operation speed while keeping device complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables faster operation of the shift register circuit, reducing signal delays and improving the resolution and speed of the display apparatus by isolating the influence of gate line loads on the carry signal, even under varying ambient conditions.
Implementation Method 1
a first transistor for supplying the first clock signal inputted to a first clock terminal to the first output terminal
Implementation Method 2
a second transistor for discharging the first output terminal
Implementation Method 3
a third transistor for supplying the first clock signal to the second output terminal
Implementation Method 4
a fourth transistor for discharging the second output terminal
Data Source
AI summary
A shift register circuit comprises a first transistor between a gate line output terminal and a clock terminal, a second transistor between the gate line output terminal and a first power supply terminal, a third transistor between a carry signal output terminal and the clock terminal and a fourth transistor between the carry signal output terminal and the first power supply terminal. Gates of the second and fourth transistors are connected to each other. A fifth transistor connected between a gate of the first transistor and a second power supply terminal and a sixth transistor connected between a gate of the third transistor and the second power supply terminal have gates both of which are connected to an input terminal. With this constitution, it is possible to suppress an influence between two synchronous output signals outputted from the shift register circuit.