Shift Register Unit Carry Signal Output Stability
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Solution Overview
Problem
Conventional gate driving circuits face complexity and noise issues due to a large number of clock signals and transistors, leading to insufficient driving capability and stability problems when applying input signals to next-level shift register units.
Innovation Solution
A shift register unit with a simplified structure, incorporating input, pull-up, pull-down, and gate driving sub-circuits, which uses a carry signal output to stabilize the gate driving signal, reducing the number of transistors and clock signal lines, and applying the input signal through a carry signal output end to prevent insufficient driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional GOA circuit is used to eliminate bonding operations and provide narrow bezel, then the display panel structure is simplified, but the circuit complexity increases and noise increases
Solution Approach 1:
The shift register unit is divided into multiple functional sub-circuits: input sub-circuitry for signal input, pull-up node control sub-circuitry for voltage regulation, pull-down node control sub-circuitry for signal control, gate driving output sub-circuitry for signal output, and carry signal output sub-circuitry for signal transmission. This segmentation allows each sub-circuit to perform a specific function with minimal transistors, reducing overall circuit complexity while maintaining the GOA technique benefits.
2Ease of manufacture
If a conventional GOA circuit is used to eliminate bonding operations and provide narrow bezel, then the display panel structure is simplified, but noise increases
Solution Approach 1:
The patent introduces a carry signal output sub-circuitry that acts as an intermediary between the input signal and the next-level shift register unit. This carry signal path is specifically designed to provide sufficient driving capability and stable signal transmission, reducing noise interference. The separate carry signal path isolates the critical signal transmission from the complex gate driving operations, thereby reducing noise.
3Device complexity
If the gate driving signal output end directly applies input signal to next-level shift register unit, then the circuit structure is simple, but driving capability is insufficient and output stability is adversely affected
Solution Approach 1:
The output function is segmented into two separate sub-circuits: gate driving output sub-circuitry that generates gate driving signals for the current stage, and carry signal output sub-circuitry that transmits the input signal to the next-level shift register unit. This segmentation ensures that the carry signal path is optimized for stable signal transmission with sufficient driving capability, while the gate driving output is optimized for gate control, thereby improving output stability without excessive complexity.
4Power
If a large quantity of clock signals and transistors are used in the gate driving circuit, then the driving capability is sufficient, but the circuit complexity increases and noise increases
Solution Approach 1:
The shift register unit uses its own internal nodes (pull-up node and pull-down node) and previously generated signals to control the timing and level of clock signals for each sub-circuit. For example, the pull-up node and pull-down node voltages directly control the switching of transistors in the input sub-circuitry and output sub-circuits, eliminating the need for external complex clock signal generation. This self-service approach maintains sufficient driving capability while minimizing circuit complexity and noise.
Data Source
AI summary
The present disclosure provides a shift register unit, including an input sub-circuitry, a pull-up node control sub-circuitry, a pull-down node control sub-circuitry, a gate driving output sub-circuitry and a carry signal output sub-circuitry. The input sub-circuitry is connected to an input end, a second clock signal input end and a pull-up node. The pull-up node control sub-circuitry is connected to the pull-up node, a pull-down node, a first clock signal input end and a first voltage input end. The pull-down node control sub-circuitry is connected to the pull-down node, the pull-up node, the first clock signal input end, the first voltage input end and a second voltage input end.