Shift Register with Charge Pump for OLED Row-Scan Driving
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Solution Overview
Problem
Existing shift registers in active matrix liquid crystal displays and OLEDs face issues with high threshold voltage loss during evaluating or resetting, leading to power consumption increases and potential circuit failures, especially when using high threshold voltage TFTs.
Innovation Solution
A shift register design incorporating a first and second thin film transistor with inverted clock signals, a third and fourth thin film transistor for reset voltage control, and a capacitor to manage gate voltages, along with a charge pump unit to ensure low gate voltage for the resetting transistor, allowing for efficient resetting and stable output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high threshold voltage TFTs are used in the shift register, then the transistor can provide sufficient current for resetting, but the threshold voltage loss during evaluating or resetting increases, leading to power consumption increases and potential circuit failures
Solution Approach 1:
The patent divides the shift register circuit into multiple functional modules: evaluating module (first transistor, first capacitor), resetting module (second transistor, third transistor, fourth transistor), and voltage control module (charge pump). This segmentation allows each module to be optimized independently - the evaluating module uses capacitive coupling to avoid threshold loss, while the resetting module uses dedicated transistors controlled by the charge pump to provide sufficient current without affecting the evaluating operation.
Solution Approach 2:
The patent introduces a charge pump as an intermediary device between the power supply and the resetting transistor. The charge pump generates a negative voltage that is applied to the gate of the resetting transistor, enabling it to provide sufficient resetting current even when using high threshold voltage TFTs. This intermediary voltage generation mechanism resolves the contradiction by providing the necessary current without increasing the threshold voltage loss in the evaluating path.
2Power
If the dimension of the TFT of the driving output is designed relatively large to handle the large load (tens of pF), then the output can be driven effectively, but the area occupied by the shift register increases
Solution Approach 1:
The patent segments the driving function into multiple specialized transistors with smaller individual dimensions. Instead of using one large TFT to handle the entire load, the circuit uses multiple smaller TFTs (first transistor for evaluating, second transistor for resetting, third and fourth transistors for voltage control) that work in sequence. This segmentation reduces the area of each individual transistor while maintaining the overall driving capability through coordinated operation.
Solution Approach 2:
The patent employs periodic clock signals to control the sequential operation of different transistor modules. The evaluating transistor operates during the evaluating phase, while the resetting transistor operates during the resetting phase, controlled by inverted clock signals. This periodic action allows smaller transistors to handle the large load capacity over time rather than requiring one large transistor to handle it simultaneously, thereby reducing the total area occupied.
3Measurement precision
If a bootstrapping method using a capacitor is used to avoid threshold loss during evaluating, then the evaluating accuracy is improved, but the circuit complexity increases
Solution Approach 1:
The patent isolates the bootstrapping capacitor into a dedicated evaluating module that is separate from the resetting module. The first capacitor is connected specifically to the gate of the first transistor for evaluating, while the resetting function is handled by a separate module with its own transistors and charge pump. This segmentation allows the bootstrapping method to be applied only where needed for evaluating accuracy, without complicating the resetting circuitry.
4Area of stationary object
If the row-scan driving circuit is implemented by using dynamic shift registers to achieve compact structure and small area, then the area is reduced, but the power consumption increases and the operating frequency band is limited
Solution Approach 1:
The patent implements a static shift register with segmented functional modules, where each module (evaluating, resetting, voltage control) is optimized for its specific function. This static design with clear segmentation avoids the continuous charging and discharging of capacitors inherent in dynamic shift registers, thereby reducing power consumption while maintaining a compact structure through efficient layout of the segmented modules.
Solution Approach 2:
The patent uses a charge pump to continuously generate and maintain the negative voltage required for the resetting transistor operation. This continuous voltage generation ensures that the resetting transistor can always provide the necessary current when needed, without requiring repeated charging cycles. This continuity of useful action reduces power consumption compared to dynamic shift registers that require periodic refreshing, while the static nature of the circuit allows for a compact implementation.
Data Source
AI summary
The present invention discloses a shift register and a row-scan driving circuit including the same, the shift register comprising a first thin film transistor, a second thin film transistor used as an evaluating transistor, a third thin film transistor, a fourth thin film transistor used as a resetting transistor, a first capacitor and a reset voltage controlling unit, wherein the reset voltage controlling unit is used to control the gate voltage of the fourth thin film transistor, so that the gate voltage of the fourth thin film transistor is pulled down to a low level corresponding to a voltage input from a low voltage signal input when a signal input from a first clock signal input is at low level, a signal input from a second clock signal input is at high level and a signal input from a signal input is at high level.