Shift Register Circuit Alternating Reference Voltages
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Solution Overview
Problem
Existing gate drivers with cascaded shift register units face issues due to transistors being in a direct current (DC) biased state, leading to threshold voltage drift and reduced transistor lifetime, causing anomalies in generated gate drive signals.
Innovation Solution
A shift register circuit design that alternates between two reference voltages with opposite phases, allowing control circuits to operate intermittently, preventing continuous DC biasing and maintaining stable transistor characteristics, comprising input, first, and second control circuits, and an output circuit connected to a clock terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are kept in a DC biased state to maintain continuous operation of the shift register unit, then the gate driver can continuously generate gate drive signals, but the transistor lifetime is reduced and threshold voltage drift occurs
Solution Approach 1:
The patent applies periodic action by alternating between two reference voltages (first reference voltage and second reference voltage) with opposite phases. The control circuits switch between these two reference voltages periodically, causing the transistors to experience alternating biasing states rather than continuous DC biasing. This periodic switching allows transistors to rest and recover between active periods, extending their lifetime while maintaining continuous gate drive signal generation through the cascaded shift register units.
2Productivity
If transistors are kept in a DC biased state to maintain continuous operation, then the gate driver can continuously generate gate drive signals, but threshold voltage drift occurs causing signal anomalies
Solution Approach 1:
The patent uses periodic action with alternating reference voltages to prevent threshold voltage drift. By switching between the first reference voltage (first polarity) and the second reference voltage (second polarity, opposite to the first), the transistors experience periodic reversal of biasing conditions. This prevents the accumulation of threshold voltage drift that occurs under continuous DC biasing, thereby maintaining stable transistor characteristics and eliminating signal anomalies while preserving continuous operation capability.
3Productivity
If control circuits operate continuously to maintain gate drive signal generation, then productivity is maintained, but transistor lifetime is reduced
Solution Approach 1:
The patent implements periodic action by designing control circuits that alternately activate using two reference voltages with opposite phases. During each period, one control circuit operates while the other is in a low-power or resting state, and then they switch roles in the next period. This periodic operation allows transistors to have active periods followed by resting periods, maintaining gate drive signal generation continuity while reducing cumulative stress on individual transistors and extending their operational lifetime.
Solution Approach 2:
The patent applies segmentation by dividing the control function into multiple control circuits that operate in an alternating fashion. Instead of a single control circuit operating continuously, the system segments the control functionality across multiple circuits that share the workload through periodic switching. This segmentation allows individual transistors to have periods of inactivity, extending their lifetime while the segmented control circuits collectively maintain continuous gate drive signal generation.
Data Source
AI summary
A shift register circuit includes an input terminal, a reset terminal, a first scan voltage terminal, a second scan voltage terminal, a first reference voltage terminal, a second reference voltage terminal, a clock terminal, an output terminal, an input circuit, a first control circuit, a second control circuit, and an output circuit. The first control circuit is configured to supply a second reference voltage applied at the second reference voltage terminal to a first node and bring the second reference voltage terminal into conduction with the output terminal in response to a second node being at an active potential. The second control circuit is configured to supply a first reference voltage applied at the first reference voltage terminal to the first node and bring the first reference voltage terminal into conduction with the output terminal in response to a third node being at an active potential.