Shift Register Circuit Dynamic Output Sub-Circuit Design

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing gate driving circuits face challenges in low temperature environments where carrier migration rates decrease, leading to reduced driving current and delayed output signals, and in high frequency states where increased driving current is needed, resulting in noise issues due to larger output transistors.

Innovation Solution

A shift register circuit with a first and second output sub-circuit that operate based on temperature and frequency conditions, where the first output sub-circuit is activated in low temperature or high frequency states to enhance driving current, and the second output sub-circuit reduces noise by operating independently in normal conditions, effectively adjusting transistor size dynamically.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the output transistor size is increased to enhance driving current in low temperature or high frequency states, then the driving ability is improved, but noise increases

Engineering Contradiction:
Improvedriving currentVSAvoidnoise
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The patent implements dynamic adjustment of the output transistor size by switching between a first output transistor and a second output transistor with different sizes based on temperature and frequency conditions. The first output transistor is used in low temperature or high frequency states to provide high driving current, while the second output transistor is used in normal states to reduce noise, achieving dynamic adaptation to different operating conditions.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If a single output transistor is used, then the circuit structure is simple, but the driving ability cannot be adapted to different temperature and frequency conditions

Engineering Contradiction:
Improvecircuit structureVSAvoidadaptation to temperature and frequency conditions
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent divides the output transistor into two separate transistors with different sizes - a first output transistor for low temperature/high frequency conditions and a second output transistor for normal conditions. This segmentation allows the circuit to adapt to different operating conditions while maintaining relatively simple control logic through a switching mechanism.

Inventive Principle:
Principle #1Segmentation

3Power

If the output transistor size is increased to enhance driving current, then the driving ability in low temperature conditions is improved, but power consumption increases

Engineering Contradiction:
Improvedriving currentVSAvoidpower consumption
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The patent dynamically switches between a first output transistor with larger size (higher power consumption but higher driving current) and a second output transistor with smaller size (lower power consumption but lower driving current) based on temperature and frequency conditions. This dynamic adjustment ensures that the larger transistor is only activated when necessary, minimizing overall power consumption while maintaining adequate driving current when needed.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10559372B2Shift register circuit, gate driving circuit, display apparatus and method for driving the same
Publication Date: 2020.02.11 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US10559372B2 patent drawing
  • US10559372B2 patent drawing
  • US10559372B2 patent drawing

AI summary

A shift register circuit includes a first output sub-circuit, and a second output sub-circuit. The first output sub-circuit is coupled to a clock signal terminal, a control signal terminal, a pull-up node and an output signal terminal, and is configured to output a clock signal output via the clock signal terminal to the output signal terminal under control of the control signal output via a control signal terminal and the potential of the pull-up node. The second output sub-circuit is coupled to the clock signal terminal, the pull-up node and the output signal terminal, and is configured to output the clock signal to the output signal terminal under control of the potential of the pull-up node.