Shift Register Circuit Internal Node Initialization
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Solution Overview
Problem
Existing shift register circuits for image display devices face issues with excessive current flow due to unsteady node potentials at power-on and require external initialization signals, which increase manufacturing costs and decrease the driving capability of pull-up transistors.
Innovation Solution
A shift register circuit design that initializes nodes to inactive levels using internal transistors and control signals, eliminating the need for external reset signals and reducing parasitic capacitance, thereby preventing excessive current flow and maintaining high driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If pull-up transistors are used with very low on-state resistance to drive gate lines, then driving capability is improved, but excessive current flows during power-on due to unsteady node potentials
Solution Approach 1:
The patent applies preliminary action by introducing an initialization circuit that sets node potentials to steady states before the clock signal is activated. The circuit includes a first transistor that charges the gate node to inactive level and a second transistor that maintains this initialized state, ensuring safe operation conditions are established in advance before normal operation begins.
2Reliability
If initializing transistors are added to prevent excessive current flow, then safety is improved, but device complexity increases
Solution Approach 1:
The patent merges the initialization function with the existing pull-up transistor structure. The first transistor serves dual purposes: it is part of the normal operation circuit and simultaneously functions as the initialization element. This integration allows the circuit to perform both normal operation and initialization without adding separate dedicated initialization transistors, thus limiting complexity increase.
3Reliability
If external initialization signals are used to reset nodes, then initialization function is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements self-service by designing the initialization circuit to automatically execute initialization when power is supplied. The circuit uses the power supply voltage itself as the initialization signal, eliminating the need for external initialization signal generation circuits. The first transistor automatically charges the gate node to inactive level based on power supply conditions, making the system self-initializing and reducing manufacturing complexity.
4Reliability
If additional initialization circuits are added, then node potential control is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by concentrating the initialization function in a localized circuit region with minimal additional components. The first and second transistors are arranged to control only the specific gate node potential, limiting the impact on overall circuit capacitance. This localized approach provides effective node potential control while minimizing the increase in parasitic capacitance compared to adding separate initialization circuits throughout the entire shift register.
Data Source
AI summary
A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.