Shift Register Circuit Parasitic Capacitance Mitigation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Shift register circuits face instability due to parasitic capacitance and frequent variations in clock signals, leading to incorrect transistor activation and output signal instability.
Innovation Solution
The circuit incorporates additional transistors and capacitors to manage voltage levels actively, ensuring stable output by configuring transistors to respond to specific voltage signals and clock signals, and using capacitors to mitigate the impact of parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional transistors and capacitors are added to actively manage voltage levels, then output signal stability is improved, but device complexity increases
Solution Approach 1:
The patent introduces a dedicated voltage signal generation circuit as an intermediary component that actively manages voltage levels at critical nodes. This circuit includes additional transistors (T1-T7) and capacitors (C1, C2) that mediate between the clock signals and the output stage, ensuring stable voltage conditions despite parasitic capacitance effects. The intermediary circuit isolates the output stage from voltage fluctuations caused by parasitic capacitance coupling.
Solution Approach 2:
The patent implements preemptive voltage level management by configuring the additional transistors and capacitors to maintain stable voltage levels at nodes N1 and N2 before problematic voltage variations can occur. The capacitors C1 and C2 are strategically positioned to cushion against voltage fluctuations caused by parasitic capacitance, ensuring that voltage levels remain within acceptable ranges even when clock signals switch frequently.
2Reliability
If transistors are configured to respond to specific voltage signals and clock signals, then incorrect activation is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by configuring specific transistors with dedicated control connections to specific nodes. Each transistor (T1-T7) is strategically positioned and connected to respond to specific voltage conditions at specific nodes (N1, N2, N3, N4). This localized control ensures that each transistor activates only under the correct voltage conditions, preventing incorrect activation while maintaining manufacturability through systematic placement.
Solution Approach 2:
The patent segments the shift register circuit into distinct functional blocks with dedicated transistors for specific functions: voltage level detection, clock signal distribution, and output control. This segmentation allows each transistor to be optimized for its specific function and simplifies the manufacturing process by providing clear design guidelines for transistor placement and connection.
Data Source
AI summary
A display panel, a stage circuit, and a driving method of the stage circuit are provided. The stage circuit includes cascaded shift register circuits. Each cascaded shift register circuit includes: a first control module, a second control module, and an output module. The first control module receives an input signal and a charging signal, and generates a voltage signal at a second node in response to a first clock signal and a voltage signal at a first node. With an exception of a first stage cascaded shift register circuit, a first transistor of a current stage cascaded shift register circuit has a first end connected to a signal output terminal of a previous stage cascaded shift register circuit, a second end connected to the second node, and a control end connected to the first node.