4-Phase Shift Register Circuit for Low Power and High Yield
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Solution Overview
Problem
Existing shift register circuits for active matrix organic light emitting displays face challenges in achieving low power consumption and high reliability while minimizing the number of thin film transistors (TFTs) per stage, with dynamic shift registers having low operable frequencies and high power consumption, and static shift registers requiring many TFTs.
Innovation Solution
A 4-phase shift register circuit is designed with n stages connected to a start pulse input line and 3 out of 4 sequentially phase-shifted clock signals, utilizing PMOS transistors and capacitors to ensure low power consumption and improved manufacturing yield by maintaining complementary logic levels on input nodes, reducing unnecessary transistor activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a dynamic shift register is used, then the number of TFTs per stage is reduced and the structure is simplified, but the operable frequency range is limited and power consumption increases
Solution Approach 1:
The patent implements a 4-phase clocking system where clock signals are applied periodically to control the shift register stages. This periodic action enables the circuit to operate efficiently at lower frequencies while maintaining dynamic operation benefits, resolving the contradiction between simplified structure and frequency limitations.
Solution Approach 2:
The patent changes the operating parameters by introducing 4-phase clocking and optimizing the TFT switching timing. This allows the dynamic shift register to operate over a wider frequency range with reduced power consumption, as the parameter changes optimize the charge storage and transfer efficiency.
2Reliability
If a static shift register is used, then the operable frequency range is widened and power consumption is reduced, but the number of TFTs per stage increases
Solution Approach 1:
The patent segments the shift register into multiple stages, each controlled by specific phases of the 4-phase clock system. This segmentation allows each stage to use fewer TFTs while maintaining reliable operation across a wide frequency range, as the segmentation distributes the functionality across phases rather than requiring all functions in each stage.
Solution Approach 2:
The patent creates a universal shift register design that can operate across wide frequency ranges by using multi-functional TFTs that perform multiple roles depending on the clock phase. This universality reduces the total number of TFTs needed per stage while maintaining reliability across different operating frequencies.
3Device complexity
If NMOS transistors are used in the shift register, then the circuit can be simplified, but charge storage from previous logic inputs is lost and reliability deteriorates
Solution Approach 1:
The patent introduces capacitors as intermediary elements that store charge between logic stages. These capacitors act as mediators that retain the charge representing previous logic inputs, preventing charge loss while maintaining circuit simplicity. The capacitors bridge the gap between NMOS transistor simplicity and reliable charge storage.
Data Source
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AI summary
A shift register circuit that improves yield, reduces cost, and embodies a pull-swing drive and low power consumption is disclosed. The shift register is a 4-phase shift register circuit comprising a plurality of PMOS transistors, and capacitors. The shift register circuit includes n (n is integer) register stages, and each register stage is connected to a start pulse input line or an output voltage line of a previous register stage, and is connected to three of four clock signal supply lines. Each of the n register stages comprises circuitry ensuring that the output stage of each register stage drives the output to either of first and second power supplies, but not both.