Shift Register Clear Signal for Anomalous Sync Detection
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Solution Overview
Problem
Conventional shift registers in display panel driving circuits suffer from anomalies in sync signals, leading to display disorders and increased power source load, and require a larger circuit area due to the need for a dummy shift circuit for resetting.
Innovation Solution
A display panel drive circuit with a shift register that includes unit circuits connected in stages, receiving a sync signal, a clock signal, and a clear signal. The clear signal is activated upon detecting anomalousness in the sync signal, stopping pulse output until the subsequent vertical scanning period starts, and eliminates the need for a dummy stage, thereby reducing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy shift circuit is added for resetting the shift register, then the shift register can be reset properly, but the circuit area increases
Solution Approach 1:
The patent merges the reset function into the existing shift register structure by using the clear signal input terminal that is already present in each shift circuit. Instead of adding a separate dummy shift circuit, the clear signal is distributed to all shift circuits through the existing input terminals, combining the reset functionality with the existing shift register architecture.
Solution Approach 2:
The clear signal input terminal, which was originally designed for a specific purpose, is made universal by connecting it to all shift circuits in the shift register. This single clear signal serves multiple shift circuits simultaneously, providing a multi-functional solution that resets the entire shift register without requiring additional dedicated reset circuits for each stage.
2Productivity
If the shift register continues operating after sync signal anomalies, then the circuit remains functional, but display disorders occur and power source load increases
Solution Approach 1:
The patent implements feedback by monitoring the sync signal for anomalies and using this information to control the clear signal. When an anomaly is detected in the sync signal, the feedback mechanism activates the clear signal, which then stops the shift register operation to prevent display disorders and excessive power consumption, creating a closed-loop control system.
Solution Approach 2:
The patent applies preliminary anti-action by detecting sync signal anomalies before they can cause harmful effects. The clear signal is activated in advance when anomalies are detected, preventing the propagation of erroneous signals that would otherwise cause display disorders and increased power source load, thereby counteracting potential harm before it occurs.
Data Source
AI summary
A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.