Shift Register Clock Control for Low-Noise Gate Driver Output
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Solution Overview
Problem
Liquid crystal display shift registers experience significant circuit noise due to clock signals, leading to improper operation of thin film transistors and abnormal circuit functioning, particularly during periods when no scanning signal should be output.
Innovation Solution
A shift register design incorporating a clock control unit, inverting unit, and pulling-down unit to manage clock signals, ensuring the output terminal remains in a discharging state and at a low level when not outputting a gate driving signal, thereby eliminating voltage-coupled noise and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the shift register outputs the clock signal continuously at the output terminal, then the scanning signal can be generated for all clock cycles, but voltage-coupled noise is generated during periods when no scanning signal should be output
Solution Approach 1:
The patent implements periodic action by controlling the clock signal output based on scanning period requirements. The clock control unit enables the output terminal to output the clock signal only during periods when scanning signals need to be generated, and disables it during periods when no scanning signal should be output. This periodic enable/disable mechanism eliminates voltage-coupled noise while maintaining scanning signal generation efficiency.
2Object-generated harmful factors
If the output terminal remains in a discharging state during non-scanning periods, then voltage-coupled noise is eliminated, but the circuit complexity increases due to additional control units
Solution Approach 1:
The patent applies multi-functionality by designing the clock control unit to serve multiple purposes: it controls the output of scanning signals during scanning periods and simultaneously controls the discharging state during non-scanning periods. The pulling-down unit is activated by the same control logic to ensure the output terminal remains at a low level. This unified control approach eliminates voltage-coupled noise while minimizing the increase in circuit complexity.
3Device complexity
If the shift register operates without additional control units, then the circuit is simpler, but the output terminal generates fluctuated levels causing circuit noise
Solution Approach 1:
The patent implements feedback by using the scanning signal generation state to control the clock signal output and the pulling-down unit. The clock control unit receives feedback about whether the output terminal should be generating scanning signals, and accordingly adjusts the clock signal output and pulling-down unit activation. This feedback mechanism ensures the output terminal remains stable during non-scanning periods while maintaining simplicity.
Data Source
AI summary
Disclosed are a shift register, a gate driver and a display device, which relate the field of display technology and may eliminate the voltage coupled noise generated by a clock signal at an output terminal of the shift register effectively. The shift register comprises: a first input unit, a clock control unit, a second input unit, an inverting unit, a pulling-down unit and a first level selecting unit, a second level selecting unit, a third level selecting unit; the first input unit is connected with a first input signal terminal, the first level selecting unit and the second input unit, respectively, wherein a node at which the first input unit is connected with the second input unit is a pulling-up node, the first input unit is used for controlling a potential at the pulling-up node. The embodiments of the present disclosure may be applied to various display devices.