Shift Register Clock Control for Noise Elimination
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Solution Overview
Problem
Liquid crystal display shift registers experience significant circuit noise due to clock signals, leading to improper operation of thin film transistors and abnormal circuit functioning, particularly during periods when no scanning signal should be output.
Innovation Solution
A shift register design incorporating a clock control unit, inverting unit, and pulling-down unit to manage clock signals, ensuring the output terminal remains in a discharging state and at a low level when not outputting a gate driving signal, thereby eliminating voltage-coupled noise and enhancing stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the shift register outputs clock signals continuously to drive scanning, then the scanning function is maintained, but voltage-coupled noise is generated causing circuit abnormalities
Solution Approach 1:
The patent extracts the harmful clock signal from the output terminal during periods when scanning signal should not be output. The clock control unit selectively blocks the clock signal from reaching the output terminal, separating the useful scanning signal generation function from the harmful noise generation, thereby eliminating voltage-coupled noise while maintaining scanning functionality.
Solution Approach 2:
The patent introduces dynamic control of the clock signal transmission through the clock control unit. The transmission state of the clock signal is changed from continuous to selective based on the scanning period, allowing the system to adapt its behavior dynamically - enabling clock signal transmission during scanning periods and blocking it during non-scanning periods to eliminate noise.
2Device complexity
If the output terminal is left floating during non-scanning periods, then circuit complexity is reduced, but voltage-coupled noise occurs and stability deteriorates
Solution Approach 1:
The patent introduces the clock control unit as an intermediary component between the clock signal source and the output terminal. This intermediary selectively mediates the clock signal transmission, blocking it during non-scanning periods to prevent noise while maintaining a relatively simple circuit structure. The clock control unit acts as a gatekeeper that maintains reliability without significantly increasing complexity.
Solution Approach 2:
The patent applies preliminary action by actively controlling the output terminal state before noise can affect the circuit. The clock control unit proactively blocks the clock signal during non-scanning periods, preventing voltage-coupled noise from occurring in the first place, rather than reacting after noise has caused problems. This preliminary preventive action maintains stability without requiring complex noise filtering circuits.
3Device complexity
If the shift register operates without noise suppression, then device complexity is minimized, but thin film transistors in pixel units turn on improperly
Solution Approach 1:
The patent extracts the harmful clock signal from the output terminal during non-scanning periods, separating the useful scanning function from the harmful noise that causes pixel unit maloperation. By removing the noise source rather than filtering it, the patent maintains simple circuit structure while preventing improper transistor switching.
Solution Approach 2:
The patent converts the potentially harmful continuous clock signal into a beneficial selective signal by using the clock control unit. The same clock signal that could cause noise and improper transistor switching is transformed into a controlled scanning signal that only outputs during appropriate periods, turning a harmful continuous signal into a beneficial periodic scanning signal.
Data Source
AI summary
Disclosed are a shift register, a gate driver and a display device, which relate the field of display technology and may eliminate the voltage coupled noise generated by a clock signal at an output terminal of the shift register effectively. The shift register comprises: a first input unit, a clock control unit, a second input unit, an inverting unit, a pulling-down unit and a first level selecting unit, a second level selecting unit, a third level selecting unit; the first input unit is connected with a first input signal terminal, the first level selecting unit and the second input unit, respectively, wherein a node at which the first input unit is connected with the second input unit is a pulling-up node, the first input unit is used for controlling a potential at the pulling-up node. The embodiments of the present disclosure may be applied to various display devices.