Bidirectional Shift Register Layout With Reduced Clock Coupling
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Solution Overview
Problem
Conventional bidirectional shift registers in display technologies face high power consumption due to inverter structures and clock coupling effects, leading to unstable output waveforms.
Innovation Solution
A shift register design with a serial connection of stages, utilizing MOS thin film transistors and capacitors to manage clock signals and supply voltages, eliminating inverter structures and reducing power consumption by coupling the drain of the outputting transistor to the high voltage supply, thereby minimizing clock coupling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If inverter structures are used in conventional bidirectional shift registers, then the circuit can provide signal inversion and driving capability, but power consumption increases and output waveform stability deteriorates due to clock coupling effects
Solution Approach 1:
The patent removes the inverter structure from the shift register circuit. Specifically, the output stage consists of transistors Q1, Q2, and Q3 directly driving the output node, without an inverter between the logic stage and output. This extraction eliminates the source of clock coupling effects and reduces power consumption while maintaining proper signal levels through alternative transistor configuration.
Solution Approach 2:
Instead of using a traditional inverter to achieve signal inversion, the patent inverts the approach by using the transistor switching network itself to directly produce the inverted output signal. The logic stage transistors (Q1, Q2, Q3) are configured to directly generate the complementary output without requiring a separate inverter stage, thereby eliminating clock coupling while maintaining inversion functionality.
2Reliability
If inverter structures with capacitive loads are used, then signal driving capability is provided, but clock coupling effects increase causing unstable output waveforms
Solution Approach 1:
The patent extracts and removes the inverter structure that was generating clock coupling effects. The output stage is reconfigured to use transistors Q1, Q2, and Q3 that directly drive the output node without the capacitive coupling inherent in inverter structures, thereby eliminating the harmful clock coupling effects while maintaining signal driving capability.
3Use of energy by moving object
If conventional shift register stages are used with inverters, then the circuit complexity is manageable, but power consumption is high
Solution Approach 1:
The patent merges the inverter function into the main logic stage by integrating the inversion operation directly into the transistor switching network (Q1, Q2, Q3). This consolidation eliminates the need for a separate inverter stage, reducing overall circuit complexity while simultaneously reducing power consumption by removing the additional switching activity and capacitive loading of a dedicated inverter.
Data Source
AI summary
A shift register comprising a plurality of shift register stages {SN}, N=1, 2, . . . , M, M being a nonzero positive integer. Each of the plurality of shift register stages, SN, comprises a first input, a second input, a third input for receiving a first clock signal CK, a fourth input for receiving a second clock signal XCK, an output for providing an output signal OUT(N), therefrom. The plurality of stages {SN} is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N−1)-th shift register stage SN−1 for receiving an output signal OUT(N−1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage, SN+1 for providing the output signal OUT(N+1) thereto.