Shift Register Clock Divider for Precise Duty Ratio
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Solution Overview
Problem
Existing clock divider circuits face challenges in generating non-overlapping N phases with a precise 1/N duty ratio at high operating frequencies due to large load capacitances from decoding logic and unbalanced load capacitances from counter reset circuitry, leading to phase overlap and duty ratio deviations.
Innovation Solution
A clock frequency divider using a counter and an N-bit shift register generates a pulse with a 1/N duty ratio every N clock cycles, ensuring balanced load capacitances and precise duty ratio, independent of fault state detection and reset circuitry, allowing for higher operating frequencies with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a counter and decoder are used to generate N phases of divide-by-N clocks, then the duty ratio can be controlled, but the large load capacitances from the decoding logic decrease the maximum operating frequency
Solution Approach 1:
The patent extracts the phase generation function from the decoder and implements it using a shift register. The shift register receives a single input signal and distributes it to N outputs with 1/N duty ratio, eliminating the need for complex decoding logic and its associated large load capacitances that limited the maximum operating frequency.
Solution Approach 2:
The patent uses a shift register to create N copies of the same timing signal, each shifted in time relative to the others. This copying approach generates the required N phases without requiring a decoder to interpret counter outputs, thereby reducing load capacitance and enabling higher operating frequencies while maintaining precise 1/N duty ratio.
2Measurement precision
If a counter and decoder are used to generate N phases, then phase control is achieved, but unbalanced load capacitances from the counter reset circuit and decoder cause the phases to overlap and duty ratio to deviate from 1/N at high frequencies
Solution Approach 1:
The patent removes the decoder and its associated unbalanced load capacitances from the phase generation path. By using a shift register that receives a single input and distributes it uniformly to N outputs, the design eliminates the source of unbalanced load capacitances that caused phase overlap and duty ratio deviation at high frequencies.
Solution Approach 2:
The patent changes the fundamental parameter of how phases are generated - instead of using a decoder that interprets counter outputs (creating unbalanced loads), the shift register approach uses a uniform distribution model where a single input signal is shifted and distributed evenly across N outputs, ensuring balanced load capacitances and reliable phase non-overlap at high frequencies.
Data Source
AI summary
A divide-by-N clock frequency divider producing N non-overlapping clocks each with precise 1/N duty ratio is implemented by a counter, a token generator and N-bit shift register. Every N clock cycles, a pulse is generated as a token from a logical combination of signals from the counter. The pulse is passed along a shift register having balanced load capacitances under control of the clock edge, ensuring a precise 1/N duty ratio that is unaffected by load capacitances from the fault state detection and/or reset circuitry. In this manner, a higher operating frequency may be achieved with low power consumption.