Shift Register Clock Gating for Low-Power Partial-Width Storage
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Solution Overview
Problem
Conventional shift registers consume energy even when unused flip-flops are not involved in data storage, leading to inefficiency.
Innovation Solution
A shift register design that enables disabling unused flip-flops through clock and power gating techniques based on input data, entering a low power mode when upper bits are not needed for computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If all flip-flops in the shift register are kept active, then data storage capacity is maintained, but energy consumption increases
Solution Approach 1:
The shift register dynamically adjusts its operational state by selectively enabling or disabling flip-flops based on the actual data width required for computation. The gating circuit responds to input data characteristics and dynamically reconfigures the active portion of the shift register, transitioning between different operational modes (full-width vs. partial-width operation) to optimize energy consumption while maintaining necessary data storage capacity
Solution Approach 2:
The invention applies different operational states to different portions of the shift register. Instead of uniformly keeping all flip-flops active, the gating circuit selectively activates only the necessary subset of flip-flops corresponding to the actual data width, while placing unused flip-flops in a low-power disabled state. This local differentiation of operational quality reduces overall energy consumption
2Loss of energy
If unused flip-flops are disabled to save energy, then power consumption decreases, but data processing capability may be affected
Solution Approach 1:
The gating circuit incorporates feedback mechanisms that monitor the actual data width and computation requirements, then use this information to control the enabling/disabling of flip-flops. The system continuously adapts its power state based on feedback about the actual computational needs, ensuring that data processing efficiency is maintained while minimizing power consumption by disabling only truly unused resources
Solution Approach 2:
The gating circuit performs preliminary assessment of the input data characteristics before the main data processing operation begins. By evaluating the data width and computation requirements in advance, the system can pre-configure the appropriate subset of flip-flops to be active, avoiding the need to keep all flip-flops powered throughout the entire operation cycle
Data Source
AI summary
The disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of sequential logic circuit that handles upper bits of input data. The shift register includes a sequential logic circuit and a gating circuit. The sequential logic circuit (e.g., flip flops) is configured to receive an input data. The gating circuit is configured to disable the portion of the sequential logic circuit for storing a portion of the input data according to data currently being stored in the sequential logic circuit during a writing cycle for writing the entire input data to the shift register.