Shift Register Circuit Clock Noise Suppression
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Solution Overview
Problem
Conventional shift register circuits in display devices suffer from defective operation due to clock noise, especially when thin film transistors with depression characteristics are used, leading to increased potential in internal nodes and subsequent stages, which affects the reliability and definition of high-resolution displays.
Innovation Solution
A shift register circuit design that includes an internal node precharging unit, an internal node pulling down unit, and an output node pulling down unit, utilizing transistors with specific clock signal phases to manage the electrical connection and disconnection of internal and output nodes, ensuring the internal node is pulled down securely and maintaining the output control transistor in an off state during unselected periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thin film transistors with depression characteristics are used in the shift register circuit, then low power consumption and high definition are achieved, but clock noise causes defective operation due to increased potential in internal nodes
Solution Approach 1:
The patent applies preliminary anti-action by introducing a pull-down transistor that actively counteracts the potential increase caused by clock noise before it can cause defective operation. The pull-down transistor is configured to turn on in response to clock noise detection and actively pull down the internal node potential, preventing the harmful effect from propagating through the circuit stages.
Solution Approach 2:
The patent uses an intermediary element (the pull-down transistor) between the internal node and the noise source to mitigate the harmful effect. This intermediary transistor acts as a buffer that can quickly respond to potential increases and discharge them, thereby protecting the subsequent circuit stages from clock noise without affecting the normal operation of the shift register.
2Device complexity
If conventional unit circuit configuration is used, then circuit simplicity is maintained, but defective operation occurs due to inability to suppress clock noise in internal nodes
Solution Approach 1:
The patent segments the unit circuit into distinct functional blocks: the original shift register components and the added pull-down transistor as a separate noise suppression module. This segmentation allows the circuit to maintain its basic shift register functionality while adding targeted noise suppression capability with minimal impact on overall circuit complexity.
Solution Approach 2:
The patent introduces dynamic control by making the pull-down transistor's conductivity state variable rather than fixed. The transistor dynamically switches between on and off states based on the detection of clock noise, allowing the circuit to adapt its noise suppression behavior to operational conditions without permanently increasing complexity.
3Ease of operation
If internal node potential is not controlled during unselected periods, then circuit operation is simplified, but leakage current increases and affects subsequent stages
Solution Approach 1:
The patent applies preliminary action by proactively controlling the internal node potential through the pull-down transistor during unselected periods before leakage current can significantly affect subsequent stages. This preliminary control prevents the accumulation of harmful potential that would otherwise lead to defective operation in downstream circuit elements.
Data Source
AI summary
A shift register circuit can achieve high definition of a display device with the smallest possible number of elements without causing defective operation.A unit circuit is provided with a thin film transistor functioning as an output control transistor; a thin film transistor precharging an internal node based on an on-level signal outputted from an output terminal of a previous stage; two thin film transistors provided in series with each other between the output terminal of the previous stage and the internal node of this stage; a thin film transistor provided between the internal node and an output terminal; and a thin film transistor pulling down the output terminal. The thin film transistors go to an on state only for a quarter period of a clock cycle which is a part of a period during which the output terminal of the previous stage is pulled down.