Shift Register Clock Noise Elimination via Periodic Discharge

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Solution Overview

Problem

Liquid crystal display shift registers experience significant circuit noise due to clock signals, leading to improper activation of thin film transistors and abnormal circuit functioning, particularly during periods when no scanning signal should be output.

Innovation Solution

A shift register design incorporating a pulling-up unit, clock control unit, resetting unit, inverting unit, and pulling-down unit, utilizing thin film transistors to control and insulate clock signals, ensuring the output terminal remains in a discharging state and at a low level when not outputting a gate driving signal, thereby eliminating voltage coupled noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the clock signal is continuously applied to the shift register output terminal, then the shift register can respond to clock cycles, but circuit noise occurs on the gate line and thin film transistors may turn on improperly

Engineering Contradiction:
Improveresponse speedVSAvoidcircuit noise
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent applies periodic action by controlling the output terminal to discharge only during specific clock cycles when scanning signals should be output, rather than continuously. The switching control unit selectively activates the discharge transistor based on the clock signal phase, creating a periodic discharge pattern that coincides with the required scanning signal output timing, thus eliminating noise during non-output periods while maintaining response during active periods

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent extracts the harmful clock signal effect from the output terminal by introducing a separate discharge path controlled by the switching control unit. The discharge transistor is specifically activated to remove clock signal influence during periods when scanning signals should not be output, effectively separating the clock signal function from the output terminal behavior and preventing noise coupling

Inventive Principle:
Principle #2Taking out (Extraction)

2Object-affected harmful factors

If the output terminal remains in a discharging state, then voltage coupled noise is eliminated, but the shift register cannot output scanning signals

Engineering Contradiction:
Improvevoltage coupled noiseVSAvoidscanning signal output
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent applies dynamics by making the discharge state controllable rather than static. The switching control unit dynamically adjusts the discharge transistor activation based on the clock signal phase and scanning requirements. During periods when scanning signals should be output, the discharge transistor is deactivated to allow normal signal output; during other periods, it is activated to maintain a discharging state and eliminate noise

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses feedback by having the switching control unit monitor the clock signal phase and the scanning signal requirements to control the discharge transistor. The control logic receives information about the current operating state and adjusts the discharge function accordingly, ensuring that the discharge is activated only when it will not interfere with scanning signal output, thus resolving the contradiction between noise elimination and signal output

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2743931B1Shift register, gate driver and display device
Publication Date: 2020.08.26 BOE TECHNOLOGY GROUP CO LTD
  • EP2743931B1 patent drawingFigure 1~2
  • EP2743931B1 patent drawingFigure 3~4
  • EP2743931B1 patent drawingFigure 5~6

AI summary

Provided are a shift register, a gate driver and a display device capable of eliminating voltage coupled noise generated at an output terminal of the shift register effectively. The shift register comprises a pulling-up unit, a clock control unit, a resetting unit, an inverting unit and a pulling-down unit; the pulling-up unit is connected with a shift trigging signal terminal, a high level signal terminal and the resetting unit, respectively; the clock control unit is connected with the pulling-up node, a clock signal terminal and the pulling-down unit, respectively; the resetting unit is connected with a reset signal terminal, a low level signal terminal, the pulling-up node and the output terminal, respectively; the inverting unit is connected with the high level signal terminal, the low level signal terminal, the pulling-up node and the pulling-down unit, respectively; the pulling-down unit is connected with the pulling-up node, the pulling-down node, the low level signal terminal, the shift trigging signal terminal and the output terminal.