Shift Register Unit Clock Terminal Sharing for OLED GOA Circuit
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Solution Overview
Problem
In OLED display devices, the Gate Driver On Array (GOA) technology requires multiple cascaded shift registers, leading to increased complexity and space occupation due to the need for separate clock signal terminals for each shift register, which complicates the circuit and wiring.
Innovation Solution
A shift register unit is designed with a first and second shift register, where the first shift register generates two control output signals based on a single clock signal, allowing the second shift register to operate without a dedicated clock signal terminal, reducing wiring and space requirements by connecting pull-down nodes between the two registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each shift register is equipped with a dedicated clock signal terminal, then the operation reliability of each shift register is improved, but the device complexity and wiring complexity increase
Solution Approach 1:
The patent merges the clock signal input functionality by making the clock signal terminal of the second shift register share the same physical terminal as the first shift register. The clock signal line is branched to supply clock signals to both shift registers simultaneously, eliminating the need for separate dedicated clock signal terminals for each shift register while maintaining proper operation of both registers
Solution Approach 2:
The clock signal terminal serves multiple functions by being shared between the first shift register and the second shift register. This single terminal performs the role of providing clock signals to both registers, making it a multi-functional terminal that reduces overall system complexity
2Productivity
If multiple cascaded shift registers are used in GOA technology, then the driving capability for pixel rows is improved, but the occupied space increases
Solution Approach 1:
The patent combines multiple shift registers into a compact cascaded structure where the first and second shift registers are closely integrated. By sharing the clock signal terminal and optimizing the interconnection between registers, the overall area occupied by the gate driving circuit is reduced while maintaining the multi-stage driving capability needed for pixel row control
3Manufacturing precision
If separate clock signal terminals are provided for each shift register, then the control precision of each register is improved, but the ease of manufacture deteriorates
Solution Approach 1:
The patent merges the clock signal distribution by using a single shared terminal that branches to multiple shift registers. This approach simplifies the manufacturing process by reducing the number of terminals and interconnections that need to be fabricated, while still providing precise control signals to each register through the branched clock signal lines
Data Source
AI summary
A shift register unit and a method of driving the shift register unit, a gate driving circuit, and a display device. The shift register unit includes: a first shift register configured to generate a first control output signal (CR1) and a second control output signal (CR2) based on a signal at a first clock signal terminal (CLKD); and a second shift register configured to generate a second output signal (OUT2) based on a signal at a third clock signal terminal (CLKE2), wherein a first pull-down node (PD1_1) of the first shift register is connected to a second pull-down node (PD2_2) of the second shift register, and a second pull-down node (PD1_2) of the first shift register is connected to a first pull-down node (PD2_1) of the second shift register.