Shift Register Node Level Stability via Control Signal Timing
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Solution Overview
Problem
The output of existing shift register units in display devices is unstable, leading to abnormal display issues due to the instability of node levels, particularly the second node, which is affected by leakage currents and requires large capacitors to maintain stability, occupying additional space.
Innovation Solution
The proposed shift register unit includes an input circuit, a reset circuit, a first control circuit, and an output circuit, where the duration of the active level of the first control signal is longer than the duration of the active level of the signal at the drive output terminal, thereby increasing the conduction duration of the second clock signal to the second node, stabilizing its level without the need for large capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large capacitors are used to maintain node stability, then the stability of node levels is improved, but the occupied area increases
Solution Approach 1:
The patent changes the timing parameter of the control signal (extending its active duration) to stabilize the second node level, replacing the need for large capacitors with a temporal parameter adjustment that reduces area occupation while maintaining stability
2Reliability
If the conduction duration of the second clock signal to the second node is increased, then the stability of the second node level is improved, but the duration of the control signal must be extended
Solution Approach 1:
The extended control signal duration ensures that the second node is fully charged to the reference voltage level before the output phase begins, preventing instability and leakage current effects during the output operation by preparing the node in advance
Data Source
AI summary
A shift register unit includes: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a drive output terminal in response to a signal of the first node, and provide a second reference signal to the drive output terminal in response to a signal of the second node; where a duration of an active level of the first control signal is longer than a duration of an active level of a signal of the drive output terminal.