Shift Register Digital Counter for Image Sensor Unit Cell
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Solution Overview
Problem
Traditional image sensor unit cells face challenges in maintaining effective charge storage capacity as they shrink in size, leading to limitations in well capacitor performance and requiring complex, large, and costly digital counters for Analog to Digital Conversion (ADC) processes.
Innovation Solution
A shift register-based digital counter is introduced, which is low-cost, calibration-free, and efficient, using a Bucket Brigade Device (BBD) to propagate charge through a series of capacitors, allowing for accurate counting of integration capacitor voltage exceedances and reducing feedthrough requirements, thereby enhancing photo-charge capacity without increasing unit cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional well capacitors are used to store charge in shrinking unit cells, then charge storage capacity is maintained, but unit cell size must increase which conflicts with miniaturization requirements
Solution Approach 1:
The patent divides the charge storage function into two separate components: a small integration capacitor for actual charge accumulation and a large virtual well capacity achieved through multiple reset operations. This segmentation allows the physical capacitor to remain small while the effective storage capacity is increased through the digital counting mechanism, resolving the contradiction between charge storage capacity and unit cell size.
Solution Approach 2:
The patent introduces a comparator and digital counter as intermediary components between the integration capacitor and the readout circuit. The comparator detects when the integration capacitor voltage exceeds a reference threshold, triggering reset operations that are counted digitally. This intermediary mechanism enables the system to achieve large effective well capacity without requiring a physically large capacitor, thus maintaining small unit cell size while increasing charge storage capacity.
2Measurement precision
If complex digital counter circuits are used for ADC processes, then conversion accuracy is improved, but circuit complexity and manufacturing cost increase
Solution Approach 1:
The integration capacitor serves a dual function: it integrates photo-charge during the integration period and simultaneously acts as a reference voltage source for the comparator. When the capacitor voltage exceeds the reference threshold, it automatically triggers the reset mechanism. This self-service approach eliminates the need for external calibration circuits and reduces overall system complexity while maintaining accurate conversion through the natural charging-discharging cycle of the capacitor.
Solution Approach 2:
The patent changes the operating parameter from traditional multi-bit parallel counters to a simple up-counter that increments with each reset event. The conversion accuracy is achieved not through complex counter logic but through the precise voltage threshold comparison and the linear accumulation of reset counts. This parameter change simplifies the digital circuit while maintaining measurement precision through the analog-digital hybrid approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shift register-based digital counter effectively increases the well capacity of image sensors while maintaining a small unit cell size, improving performance for Long Wavelength Infrared (LWIR) and Medium Wavelength Infrared (MWIR) applications by accurately counting charge integrations and converting residual charges into digital signals, thus enhancing image capture efficiency.
Implementation Method 1
a photodiode, an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode responsive to an input light signal incident on the photodiode
Implementation Method 2
an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode over an integration period
Data Source
AI summary
According to one aspect, embodiments herein provide a digital unit cell comprising a photodiode, an integration capacitor coupled to the photodiode and configured to accumulate charge generated by the photodiode responsive to an input light signal incident on the photodiode over an integration period, a comparator coupled to the integration capacitor and configured to compare a voltage across the integration capacitor with a voltage reference and to generate a clock signal at a first level each time a determination is made that the voltage across the integration capacitor is greater than the voltage reference, a shift register coupled to the comparator and configured to receive the clock signal from the comparator and increase a count value each time the clock signal at the first level is received from the comparator, and an output coupled to the shift register and configured to provide the count value to an external system.