Shift Register Unit Coupling Noise Prevention
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Solution Overview
Problem
Conventional shift register units in display panels suffer from coupling noise and image flickers due to deteriorated thin-film transistors, leading to malfunctions as the driving voltage increases over time, especially with the JUST scheme where clock signals do not overlap, causing incorrect multiple-outputs of gate drive signals.
Innovation Solution
A method and circuit design for a shift register unit in a multi-stage gate driving circuit that includes a capacitor between the pull-up node and the gate-drive signal output port, with specific control sub-circuits and clock signal timing to prevent coupling noise by setting the pull-down node to turn-on voltage during the rising edge of the n-th clock signal and resetting the potential level of the gate-drive signal output port to turn-off voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the JUST scheme is used where clock signals are inputted sequentially without overlap, then the gate drive signals can be generated efficiently, but coupling noise is generated causing incorrect multiple-outputs of gate drive signals
Solution Approach 1:
The patent applies preliminary action by setting the pull-down node to turn-on voltage level before the main clock signal transition. Specifically, the pull-down control sub-circuit is activated in advance during the rising edge of the n-th clock signal, ensuring the pull-down node is ready to prevent coupling noise before it can cause incorrect multiple-outputs. This proactive preparation eliminates the harmful effect while maintaining efficient signal generation.
2Object-generated harmful factors
If a TFT is used to control pull-down node potential to prevent coupling noise, then incorrect multiple-outputs can be prevented, but the TFT deteriorates over driving voltage and time reducing reliability
Solution Approach 1:
The patent changes the control parameter from using a single TFT switching mechanism to a multi-stage control approach involving both pull-up and pull-down control sub-circuits with different clock signals. The pull-down control sub-circuit uses the p-th clock signal (where p = (n+3) mod 4) while the pull-up control sub-circuit uses the m-th clock signal (where m = (n+2) mod 4). This parameter change distributes the stress on individual transistors and improves overall system reliability while maintaining noise prevention.
3Device complexity
If clock signals are inputted with no overlap between adjacent signals, then the driving process is simplified, but image flickers and malfunctions occur due to coupling noise
Solution Approach 1:
The patent introduces intermediary control nodes (pull-up node and pull-down node) that mediate between the clock signals and the gate drive output. These intermediary nodes act as buffers that prevent direct coupling noise from propagating to cause image flickers. The pull-down node, controlled by the p-th clock signal, and the pull-up node, controlled by the m-th clock signal, work together to isolate and eliminate the harmful coupling effects while maintaining a relatively simple driving process.
Data Source
AI summary
The present application discloses an N-th shift register unit circuit including at least a gate-drive signal output sub-circuit, a pull-up control sub-circuit, and a pull-down control sub-circuit respectively connected between a pull-up node and a pull-down node and provided with a p-th clock signal in addition to an n-th clock signal. A driving method includes controlling the pull-down node at turn-off voltage level when the p-th clock signal is at turn-on voltage level during which the n-th clock signal is correspondingly rising to turn-on voltage level from turn-off voltage level.