Shift Register Data Padding for Variable-Length CXL Transfer
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Solution Overview
Problem
Existing data transmission methods in Compute Express Link (CXL) face inefficiencies due to inconsistent data lengths, leading to wasted storage addresses and reduced data processing efficiency, particularly in high-speed scenarios.
Innovation Solution
A data padding method and apparatus using a shift register to uniformly process data of varying lengths by determining the space occupied by remaining data, receiving and storing input data, and outputting a portion of the combined data as unit output data, ensuring efficient data alignment and encryption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large number of storage addresses are used for data padding, then data alignment is achieved, but storage addresses are wasted and data processing efficiency is reduced
Solution Approach 1:
The invention segments the data processing into fixed-width units (N words) and uses a shift register divided into multiple storage units. Each storage unit handles a specific segment of data, allowing efficient alignment without requiring excessive storage addresses. The shift register processes data in manageable chunks rather than requiring a large contiguous address space for padding.
Solution Approach 2:
The invention changes the parameter of data width representation by using a configurable shift register with N storage units, where each unit stores N words of data. This parameter change allows the system to adapt to different data width requirements (M words input, N words output) without wasting storage addresses, as the shift register dynamically adjusts to the required data alignment rather than using fixed large address spaces.
2Productivity
If data of different lengths is processed uniformly, then data processing efficiency is improved, but complex data length conversion is required
Solution Approach 1:
The shift register is designed as a universal data processing unit that can handle data of different lengths (M words input, N words output) through a standardized architecture. The same shift register structure and control logic work for any data length conversion scenario, making the system multi-functional without requiring separate processing paths for different data types. This universality improves efficiency while managing complexity through a single versatile mechanism.
Solution Approach 2:
The invention introduces dynamic control mechanisms where the shift register's operation adapts to the specific data length requirements. The control unit dynamically determines the number of storage units to use and adjusts the shifting operation based on the input data length M and required output length N. This dynamic adaptation allows uniform processing of variable-length data without requiring complex static conversion circuits for each possible data length scenario.
3Adaptability or versatility
If the difference between input bit width and output bit width is large, then data format conversion is achieved, but data reading and writing efficiency is seriously impacted
Solution Approach 1:
The invention performs preliminary action by pre-organizing data into the shift register's N storage units before the actual conversion operation. The data is initially loaded and arranged in the shift register according to the target format (N words per unit), so that when conversion is needed, the data is already in an optimal state for efficient reading and writing. This preliminary organization eliminates the need for complex real-time conversion during data transfer, maintaining high efficiency even with large bit width differences.
Solution Approach 2:
The shift register acts as an intermediary buffer between the input data (M words) and output data (N words). It temporarily stores and reorganizes the data in its internal N-unit structure, mediating the conversion process. This intermediary approach allows the system to handle large differences between input and output bit widths efficiently, as the shift register absorbs the conversion complexity internally while presenting simple, efficient interfaces for both data input and output operations.
Data Source
AI summary
A data padding method comprises: determining a length of a space occupied by remaining data in the register; comparing the length of the space occupied; performing, when the length of the space occupied by the remaining data is less than the length of the unit input data, following operations: receiving a unit input data and storing it continuously with the remaining data in the register; determining a length of a unit output data to be output; intercepting a portion of data with a length of N words from data formed by padding the remaining data buffered in the register and the unit input data and starting from an address space of a lowest bit of the register, as the unit output data and outputting it; and shifting the data remaining in the register as a whole to an address space in the register starting from the lowest bit.