Shift Register Darlington Structure for Negative Drift

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Solution Overview

Problem

The complexity of Gate Driver on Array (GOA) technology for liquid crystal display (LCD) and organic light emitting diode (OLED) devices leads to potential negative drift due to thin film transistor characteristics, especially under negative bias temperature stress or long-term illumination, complicating the design and integration of highly reliable circuits.

Innovation Solution

A shift register design with a simplified structure, incorporating a Darlington structure with alternating inverters and a different storage capacitor location, which controls the potential of the pull-up node using a clock signal, reducing noise and enabling lossless output while maintaining voltage inversion between pull-up and pull-down nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If GOA technology is used to form gate driving circuit directly on array substrate, then integration is improved and bezel is narrowed, but negative drift occurs due to thin film transistor characteristics under negative bias temperature stress or long-term illumination

Engineering Contradiction:
ImproveintegrationVSAvoidnegative drift
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent inverts the conventional inverter structure by using a Darlington configuration where the output of the first inverter is connected to the input of the second inverter, creating an inverted signal path that compensates for negative drift in thin film transistors

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The patent introduces a feedback mechanism where the output of the second inverter is fed back to the input of the first inverter, creating a closed-loop system that stabilizes the signal and prevents negative drift accumulation over time

Inventive Principle:
Principle #23Feedback

2Device complexity

If conventional inverter structure is used, then circuit design is simple, but noise is high and output is not lossless

Engineering Contradiction:
Improvecircuit designVSAvoidnoise
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent merges two inverters into a Darlington configuration, combining their functions to achieve noise cancellation while maintaining signal integrity through the coordinated operation of both inverter stages

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent converts the inherent noise and signal loss of conventional inverters into a benefit by using the Darlington structure to cancel out these harmful effects, turning the weakness of individual inverters into the strength of the combined system

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11114010B2Shift register, method for driving same, gate driving circuit, and display device
Publication Date: 2021.09.07 HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
  • US11114010B2 patent drawing
  • US11114010B2 patent drawing
  • US11114010B2 patent drawing

AI summary

A circuit includes an input sub-circuit configured to transmit an input signal from an input signal terminal to a feedback node under control of a first clock signal from a first clock signal terminal; a pull-up node control sub-circuit configured to transmit a feedback signal of the feedback node to a pull-up node under control of a first clock signal from the first clock signal terminal; a feedback sub-circuit configured to transmit a first voltage signal from a first voltage signal terminal to the feedback node under control of the pull-up node; an output sub-circuit configured to transmit a second clock signal from a second clock signal terminal to an output signal terminal under control of the pull-up node; and a pull-down sub-circuit configured to transmit a second voltage signal from a second voltage signal terminal to the output signal terminal under control of a pull-down node.