Shift Register Output Stability via DC Charging Control
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Solution Overview
Problem
Conventional shift registers experience unstable output due to coupling phenomena caused by clock pulses, leading to undesired activation of pull-up switching devices.
Innovation Solution
A shift register design that utilizes direct current (DC) voltage to generate scan pulses, with each stage having a node controller and output unit to control charging durations and output scan pulses, incorporating switching devices and capacitors to manage voltages and prevent unwanted activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock pulses are used to generate scan pulses, then scan pulses can be generated sequentially, but coupling phenomena occur causing unstable output and undesired activation of pull-up switching devices
Solution Approach 1:
The patent extracts the harmful coupling effect by separating the charging function from the clock pulse signal. Instead of using the clock pulse directly for charging (which causes coupling), the invention introduces a dedicated charging voltage signal that is applied to the set node independently, thereby removing the source of the coupling phenomenon while maintaining the sequential scan pulse generation function.
Solution Approach 2:
The patent introduces an intermediary charging voltage signal that mediates between the clock pulses and the set node. This charging voltage acts as a buffer that transfers the timing information from clock pulses to the set node without creating direct coupling, thus preventing undesired activation of the pull-up switching device while still enabling sequential operation.
2Productivity
If clock pulses are applied to the drain electrode of the pull-up switching device, then scan pulses can be generated, but the pull-up switching device may be turned on in undesired periods
Solution Approach 1:
The patent segments the control signals for the pull-up switching device into separate functions: clock pulses control the timing and sequencing, while a dedicated charging voltage controls the actual charging of the set node. This segmentation ensures that the pull-up switching device is activated only during appropriate periods when the charging voltage is applied, preventing undesired activation while maintaining productivity.
3Productivity
If conventional clock pulse-based operation is used, then scan pulses are generated sequentially, but power consumption increases due to repeated charging and discharging
Solution Approach 1:
The patent implements continuity of useful action by maintaining the set node charge throughout the high duration of scan pulses using a dedicated charging voltage. Instead of repeatedly charging and discharging the set node with each clock pulse, the charging voltage continuously maintains the charge, reducing energy loss while preserving the sequential scan pulse output function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution stabilizes output by eliminating coupling effects, reduces power consumption by using DC voltage, and ensures proper operation of switching devices during scan pulse generation.
Implementation Method 1
Each of the stages may further include a first capacitor connected between the set node and the output terminal, and a second capacitor connected between the first preset node and the second preset node.
Data Source
AI summary
Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.