Shift Register Defective Column Skipping in Non-Volatile Memory
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Solution Overview
Problem
Existing non-volatile memory systems face inefficiencies in accessing memory due to defective columns, as current methods require extensive communication between the controller and memory, and within the controller, to manage defective columns, complicating random access and increasing processing time.
Innovation Solution
A method is introduced where a series of shift registers are used to select and skip defective columns, maintaining a count of defective columns for each loop, allowing for efficient access by determining the corresponding loop and residual column address, and offsetting the address to account for defective columns, thereby simplifying the access process and reducing the need for extensive communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller manages defective column remapping, then defective columns can be handled, but it requires extensive communication between controller and memory and increases processing time
Solution Approach 1:
The patent pre-calculates and stores the cumulative defective column counts in the memory device itself during manufacturing or initialization. This preliminary action allows the memory to independently handle defective columns during operation without requiring real-time communication with the controller for remapping calculations, thereby reducing processing time while maintaining reliable defective column handling.
Solution Approach 2:
The memory device is equipped with internal circuitry that automatically uses the stored cumulative defective column counts to calculate and output corrected column addresses. This self-service mechanism eliminates the need for the controller to manage remapping logic, reducing communication overhead and processing time while ensuring reliable handling of defective columns through the memory's own internal resources.
2Reliability
If the controller manages remapping of defective columns, then defective portions can be eliminated, but it requires extensive exchange of information between controller and memory
Solution Approach 1:
The patent extracts the remapping logic and cumulative defective column count storage from the controller and places them directly in the memory device. By taking out the complex communication and calculation functions from the controller, the system eliminates defective portions while significantly reducing the communication complexity between controller and memory, as the memory now handles these functions independently.
Solution Approach 2:
The patent introduces cumulative count data as an intermediary element stored in the memory device that mediates between the physical defective columns and the logical address space. This intermediary allows the memory to automatically translate logical addresses to physical addresses accounting for defective columns without requiring extensive back-and-forth communication with the controller, thereby reducing communication complexity while maintaining reliable defective portion elimination.
3Ease of operation
If random access is implemented with transparent defective column mapping, then access can be simplified, but determining the correct column requires offset calculations
Solution Approach 1:
The patent pre-calculates and stores cumulative defective column counts for each column group in the memory device during initialization or manufacturing. This preliminary calculation allows random access operations to simply retrieve the pre-computed offset values and apply them directly, maintaining ease of operation while avoiding complex real-time offset calculations during access operations.
Solution Approach 2:
The memory device performs the address offset calculation automatically using its internal circuitry and pre-stored cumulative defective column counts. This self-service approach simplifies random access for the controller (as it only needs to provide the base address) while the memory independently handles the complex offset calculations, effectively distributing the computational burden and maintaining ease of operation without sacrificing address calculation accuracy.
Data Source
AI summary
Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly.