Gate Driver Shift Register Topology for Narrow-Bezel Displays
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing the width of gate driver circuits, particularly the shift register, to achieve a narrower bezel without increasing signal delay, which is essential for downsizing and weight reduction in flat panel displays.
Innovation Solution
The proposed solution involves a driver circuit design that includes a shift register unit, a demultiplexer circuit, and multiple signal lines, where the shift register units are connected to each other in a specific configuration, and the demultiplexer circuits are connected to a subset of the signal lines, allowing for a reduced width of the gate driver circuit while maintaining signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the width of the shift register is reduced to narrow the bezel, then the gate driver circuit width is reduced, but the signal delay time increases
Solution Approach 1:
The shift register is divided into multiple stages (first stage, second stage, third stage, etc.), with each stage handling a portion of the signal routing. This segmentation allows the circuit to be compact while maintaining proper signal propagation paths, reducing overall width without increasing delay
Solution Approach 2:
The circuit layout transitions from a conventional planar arrangement to a folded configuration where signal lines extend in multiple directions (horizontal and vertical). This dimensional change allows efficient signal routing in a compact area, reducing circuit width while maintaining signal integrity and timing
2Area of stationary object
If the gate driver circuit is downsized to achieve a narrower bezel, then the display device size is reduced, but the circuit layout complexity increases
Solution Approach 1:
The signal lines are designed to serve multiple functions: they carry clock signals between shift register stages, provide reset signals to transistor gates, and connect to pixel electrodes. This multi-functionality reduces the number of separate wiring paths needed, simplifying the overall layout while achieving compact dimensions
Solution Approach 2:
Different regions of the circuit are optimized for specific functions: the first stage handles initial signal distribution, intermediate stages perform signal routing and resetting, and the final stage connects to pixel electrodes. This localized optimization allows each region to be efficiently designed for its specific purpose, reducing overall complexity
Data Source
AI summary
To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n−3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.