Shift Register Disable Circuit for Glitch Prevention
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Solution Overview
Problem
In active matrix liquid crystal displays, asynchronous phenomena occur due to different parasitic capacitance and resistance in the output synchronous signals, leading to output glitches that affect the normal operation and image quality.
Innovation Solution
A shift register circuit with a disable circuit and sample circuit in the first stage, which receives timing controller signals to generate and transfer correct sample signals, ensuring synchronous operation by stopping the sampling procedure when necessary, even with delayed start and clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous clock signals are transmitted through different routes to the data driver, then the timing controller can generate proper clock and start signals, but parasitic capacitance and resistance cause asynchronous phenomena and output glitches
Solution Approach 1:
The patent introduces a disable circuit as an intermediary component between the sample circuit and the output stage. This disable circuit receives the second sample signal and uses it to control the enabling of the first sample signal, thereby mediating the timing relationship between different signal paths and eliminating asynchronous phenomena caused by parasitic effects
Solution Approach 2:
The patent implements a feedback mechanism where the second sample signal from a subsequent stage is fed back to the disable circuit, which then controls the sampling operation of the first stage. This feedback loop ensures that sampling only occurs when properly synchronized with the clock signal, preventing asynchronous glitches
2Productivity
If the shift register extracts clock signal during the high-pulse period of start signal, then sample signals can be generated, but signal delay causes incorrect sampling and affects image quality
Solution Approach 1:
The patent applies preliminary action by having the disable circuit prepare the sampling stage in advance. The disable circuit is enabled before the clock signal arrives and is disabled after the clock signal passes, ensuring that the sampling circuit is ready to correctly capture the clock signal without delay-related errors
Data Source
AI summary
A shift register circuit which having a plurality of stages, a signal of the timing controller is conveyed to the shift register circuit for generating and transferring a sample signal to data latch circuit. The first stage of the shift register, comprising a disable circuit and a sample circuit, receives the signal of the timing controller and transfers a right sample signal to the data latch circuit and next stage of the shift register. The disable circuit of first stage of the shift register receives sample signal of second stage of the shift register to stop the sampling procedure of the first stage of the shift register.