Shift Register Unit for Display Gate Drive Circuit

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Solution Overview

Problem

Existing gate drive circuits in display devices have limitations that need to be improved, particularly in the design of shift register units which affect the overall performance of the display device.

Innovation Solution

A shift register unit is designed with an input subcircuit, a signal output subcircuit, and a first control subcircuit, which control voltage levels at specific nodes to manage the disconnection and conduction of clock signals and signal outputs. This design ensures that the cutoff time of the effective voltage interval of the last output signal is greater than or equal to the starting time of the effective voltage interval of the control signal, and less than the cutoff time of the control signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate drive circuit uses conventional shift register units, then the basic signal transmission function is achieved, but the falling edge time of signal outputs is prolonged causing GOA stripes and degraded display performance

Engineering Contradiction:
Improvedisplay performanceVSAvoidfalling edge time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The shift register unit is divided into multiple independent subcircuits (input subcircuit, signal output subcircuit, first control subcircuit, second control subcircuit, cascade output subcircuit) that can be independently optimized. Each subcircuit handles specific signal processing tasks, allowing precise control over signal timing characteristics to reduce falling edge time while maintaining display quality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit employs dynamic voltage control through multiple control signals (input control signal, first control signal, second control signal) that dynamically adjust the operating state of transistors. This dynamic control enables optimized signal transition timing, reducing falling edge duration and eliminating GOA stripes without sacrificing display performance

Inventive Principle:
Principle #15Dynamics

2Reliability

If the shift register unit controls voltage levels to manage disconnection and conduction, then signal transmission accuracy is improved, but the circuit structure becomes more complex

Engineering Contradiction:
Improvesignal transmission accuracyVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The complex voltage control function is segmented across multiple specialized subcircuits, each responsible for a specific aspect of voltage control. The input subcircuit handles signal input, the signal output subcircuit manages output timing, and control subcircuits handle specific control signals. This segmentation makes the complex voltage control more manageable and maintainable while improving signal transmission accuracy

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple control subcircuits use similar transistor-based voltage control mechanisms to achieve different control objectives. The control transistors in various subcircuits perform analogous functions (controlling voltage levels to manage disconnection and conduction) but are applied to different signal paths and timing requirements, providing a universal control approach that simplifies design while maintaining reliability

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12333976B2Display device, gate drive circuit, shift register unit and driving method thereof
Publication Date: 2025.06.17 HEFEI BOE ZHUOYIN TECH CO LTD
  • US12333976B2 patent drawing
  • US12333976B2 patent drawing
  • US12333976B2 patent drawing

AI summary

The present disclosure provides a display device, a gate drive circuit, a shift register unit and a driving method thereof. The shift register unit includes an input subcircuit configured to control a voltage at the first node under voltage control of the input control end; a signal output subcircuit configured to control disconnection and conduction between the clock signal ends and respective signal output ends under voltage control of the first node; a first control subcircuit configured to control the voltage at the first node under voltage control of the first control signal end.