Shift Register Layout for Narrow-Bezel Display Substrates
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Solution Overview
Problem
The existing display technologies face challenges in efficiently integrating gate driving circuits on thin film transistor array substrates due to space congestion and complex wire arrangements, which hinder the realization of a narrow frame design in display panels.
Innovation Solution
A display substrate design featuring a shift register unit with a specific arrangement of transistors and capacitors, including a first control transistor and a second control transistor with continuous active layers and gate electrodes extending in different directions, along with a voltage stabilization circuit and noise reduction transistors, to optimize space utilization and reduce congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate driving circuits are integrated on thin film transistor array substrates using conventional layouts, then the driving function is achieved, but space congestion and complex wire arrangements occur
Solution Approach 1:
The patent applies dimensionality change by arranging transistors in a three-dimensional stacked configuration rather than conventional planar layouts. Multiple transistor layers are stacked vertically with selective electrical connections, transforming a two-dimensional layout problem into a three-dimensional spatial solution. This reduces wire complexity by utilizing vertical stacking to shorten connection paths and eliminate redundant lateral wiring.
Solution Approach 2:
The patent implements nesting by placing multiple transistor layers within a compact vertical stack, where smaller functional elements are nested within larger structural frameworks. The stacked transistor architecture allows inner layers to be contained within the vertical envelope of outer layers, maximizing space utilization and reducing overall device footprint while maintaining all necessary electrical connections.
2Reliability
If conventional transistor arrangements are used in shift register units, then circuit functionality is achieved, but space efficiency is reduced and narrow frame design is hindered
Solution Approach 1:
The patent reduces shift register unit area by transitioning from planar transistor arrangements to vertical stacked configurations. Multiple transistor layers are arranged in the vertical dimension, allowing circuit elements that would traditionally require lateral spacing to instead occupy vertical space. This dimensional transformation compactly packs the shift register functionality into a smaller footprint area.
Solution Approach 2:
The patent merges multiple transistor functions into integrated stacked units where adjacent transistors share common structures such as gate electrodes, source/drain regions, or insulating layers. This merging approach consolidates what would be separate lateral components into unified vertical structures, reducing the total area required for the shift register unit while maintaining all necessary circuit functions.
Data Source
AI summary
A display substrate and manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, and a shift register unit and a first clock signal line that are on the base substrate, the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit, the shift register unit includes an input circuit, an output circuit, a first control circuit and an output control circuit, and the first control circuit includes a first control switch and a second control switch, an active layer of the first control switch and an active layer of the second control switch are a continuous control semiconductor layer, the control semiconductor layer extends along the first direction.