Shift Register Unit for Narrow Border Displays
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Solution Overview
Problem
The existing gate driving circuits in display devices have a large layout area due to their cascaded shift register units, which hinders the achievement of narrow borders and high resolution.
Innovation Solution
A shift register unit comprising two transfer gate modules, four AND gate modules, two capacitor modules, and buffer-amplifier modules, along with a specific configuration of clock and pulse signal inputs and outputs, is introduced to reduce the layout area. This configuration includes connections between nodes and signal terminals that allow for efficient signal transfer and amplification, reducing the number of required electrical devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple cascaded shift register units are used to achieve high resolution and narrow border, then the gate driving circuit can drive more pixels, but the layout area becomes large
Solution Approach 1:
The patent merges multiple shift register units into a single integrated unit that can process multiple pixels simultaneously. The gate driving circuit integrates four pixel driving functions into one unit, reducing the number of separate cascaded units needed and thereby reducing the overall layout area while maintaining high-resolution driving capability.
Solution Approach 2:
The gate driving circuit is designed with multi-functionality to drive multiple pixels (up to four pixels) from a single unit. By incorporating multiple pixel electrode connection capabilities and multi-mode operation (normal mode and half-tone mode), the circuit achieves higher productivity without requiring proportional increases in layout area.
2Area of stationary object
If the gate driving circuit layout area is reduced, then border narrowing is achieved, but signal transfer and amplification efficiency may be compromised
Solution Approach 1:
The patent employs a nested structure where capacitor modules are strategically positioned within the compact gate driving circuit layout. The first and second capacitor modules are connected to specific nodes to maintain signal levels, enabling efficient signal transfer and amplification within the reduced area by nesting functional elements optimally.
Solution Approach 2:
The patent utilizes multi-dimensional signal routing and node connections to achieve efficient signal transfer within a compact two-dimensional layout. By creating multiple connection paths and utilizing vertical stacking of circuit layers, the design maintains signal integrity and amplification efficiency without requiring increased horizontal layout area.
Data Source
AI summary
The embodiments of the present disclosure provide a shift register unit, a gate driving circuit and a driving method thereof, and a display device. The shift register unit, comprises two transfer gate modules (211, 212), four AND gate modules (231, 232, 233, 234), and two capacitor modules (241, 242), as well as a pulse signal input terminal (IN), four pulse signal output terminals (L1, L2, L3, L4), and a plurality of clock signal input terminals (CLK1 to CLK8). The shift register unit provided in the present disclosure can make the layout area occupied by the corresponding gate driving circuit reduce greatly as compared with that occupied by the gate driving circuit in the prior art, which facilitates border narrowing of the corresponding display device.