Shift Register Architecture for Display Panel GOA Circuit Layout
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Solution Overview
Problem
The complexity of high-resolution display panel designs, particularly in gate driver on array (GOA) architectures, leads to complicated circuit layouts due to the need for numerous shift register stages and increased complexity as display technology advances, making it challenging to integrate shift registers and gate drivers efficiently on a glass substrate.
Innovation Solution
A shift register architecture with multiple stages electrically coupled in series, each stage featuring a stage shift circuit and de-multiplexing circuit with specific switch configurations, including transistors and diodes, to generate scanning signals for driving multiple pixel rows, simplifying the layout and operation by optimizing the height and signal generation for each stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If each shift register stage generates scanning signals for only one pixel row (conventional GOA architecture), then the layout height of each stage matches the pixel row height H, but the number of stages required increases significantly for high-resolution displays, leading to complicated circuit layouts
Solution Approach 1:
Each shift register stage is designed to generate scanning signals for multiple pixel rows (specifically j rows) simultaneously, rather than just one row. This multi-functionality reduces the total number of stages needed from N to N/j, directly reducing circuit layout complexity while maintaining the required scanning capability for high-resolution displays
Solution Approach 2:
The patent combines the functions of multiple shift register stages into a single stage by implementing a de-multiplexing circuit that distributes one stage's output to multiple pixel rows. This merging approach consolidates the circuit structure, reducing the overall number of stages and simplifying the layout
2Ease of manufacture
If the layout height of each shift register stage is H (same as pixel row height), then the architecture follows conventional GOA design, but the overall layout becomes very complicated for high-resolution displays requiring many stages
Solution Approach 1:
Each shift register stage is designed with a layout height of j×H to accommodate the generation of scanning signals for j pixel rows. This increased height per stage enables multi-row signal generation, reducing the total number of stages and simplifying the overall layout while maintaining manufacturability through standard GOA integration techniques
3Manufacturing precision
If display technology advances requiring higher resolution, then more pixel rows need to be driven, but the conventional GOA architecture requires proportionally more shift register stages, making the design very complicated
Solution Approach 1:
The de-multiplexing circuit within each shift register stage enables a single stage to serve multiple pixel rows (j rows), creating a universal stage design that can accommodate higher resolutions without proportionally increasing the number of stages. This reduces design complexity while maintaining the precision required for high-resolution displays
Solution Approach 2:
The patent increases the layout height dimension of each shift register stage to j×H, allowing the stage to vertically accommodate circuits for generating scanning signals for j pixel rows. This dimensional change enables a single stage to handle multiple rows, reducing the number of stages needed for high-resolution displays and simplifying the overall design
Data Source
AI summary
The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.