Alternating Shift Register Gate Driving for Flexible Display Resolution
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Solution Overview
Problem
Traditional gate driving circuits with cascaded shift registers face limitations in display technology, particularly in achieving flexible resolution display without additional hardware, such as transitioning between full and low-resolution modes.
Innovation Solution
A gate driving circuit design with alternating cascaded first and second shift registers, controlled by specific clock signals and reset configurations, allowing for generation of output signals in multiple stages with adjustable duty cycles, enabling flexible resolution display by sequential or grouped scanning of sub-pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional cascaded shift registers are used in gate driving circuit, then the circuit structure is simple, but the display resolution flexibility is limited
Solution Approach 1:
The gate driving circuit is divided into multiple independent shift register units (first shift register, second shift register, third shift register, etc.), each capable of independent operation. These units can be selectively activated to achieve different display resolutions. For example, all units can operate for full resolution, or only every other unit can operate for half resolution, providing flexibility without requiring a completely different circuit design.
Solution Approach 2:
The circuit incorporates dynamic control mechanisms through clock signal management. Different clock signals (first clock signal, second clock signal, third clock signal) can be applied to different shift register units, allowing dynamic switching between full-resolution mode (all units active) and low-resolution mode (selective units active). This dynamic reconfiguration enables resolution flexibility using the same hardware infrastructure.
2Adaptability or versatility
If additional hardware is added to achieve flexible resolution display, then the adaptability improves, but the device complexity increases
Solution Approach 1:
Each shift register unit is designed with multi-functionality to serve different purposes. The same basic circuit structure can operate in full-resolution mode or be selectively activated for low-resolution mode. The circuit includes universal components like clock signal terminals, reset terminals, and output terminals that can function in multiple configurations, eliminating the need for additional dedicated hardware for resolution switching.
Solution Approach 2:
The shift register units can selectively activate themselves based on control signals. Each unit has the capability to respond to clock signals and generate output signals independently when needed. The circuit uses self-service mechanisms where the shift registers can be individually enabled or disabled through clock signal management, allowing the system to achieve resolution flexibility without requiring external control hardware for each unit.
3Manufacturing precision
If sequential scanning of sub-pixels is used, then the display resolution is high, but the scanning speed decreases
Solution Approach 1:
The display scanning is divided into multiple parallel channels through multiple shift register units. Each unit scans a portion of the sub-pixels simultaneously. For example, the first shift register scans odd-numbered sub-pixel rows while the second shift register scans even-numbered rows, enabling parallel processing that maintains high resolution while improving scanning speed.
Solution Approach 2:
The circuit enables continuous scanning operation by having multiple shift register units work in parallel. While one unit is scanning, another unit can be preparing or resetting. The clock signal distribution ensures continuous operation without idle time, maintaining high scanning speed while achieving fine resolution through the coordinated output of multiple units.
Data Source
AI summary
There is provided a gate driving circuit, a display panel and a driving method of the gate driving circuit. The gate driving circuit includes multiple stages of shift registers. The multiple stages of shift registers comprise N first shift registers arranged alternately with N second shift registers. The N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals. The N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals. K and N are both integers greater than 1, and K≤N.