Shift Register Double-Gate Transistor Threshold Voltage Drift

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Solution Overview

Problem

The existing gate driving circuit in display technologies experiences threshold voltage drift in transistors due to biased voltage stresses, leading to abnormal signal output and poor display performance, particularly in the charging and output phases of shift registers.

Innovation Solution

The proposed solution involves a shift register design with a double-gate thin film transistor and a reset circuit that alternates bias voltage stresses between adjacent image frames, using a pull-up transistor with gate electrodes controlled by two pull-up nodes, and a reset circuit with double-gate transistors to cancel out voltage drifts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single-gate transistor is used in the shift register, then the device complexity is low, but the threshold voltage drift occurs due to biased voltage stresses during charging and output phases

Engineering Contradiction:
Improvetransistor structure complexityVSAvoidthreshold voltage stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The single gate electrode is segmented into two separate gate electrodes (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows the transistor to have different gate voltages applied to each gate, enabling compensation for threshold voltage drift by adjusting the voltage on one gate relative to the other, thus improving reliability without significantly increasing overall device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention changes the electrical parameters by applying different voltages to the two gate electrodes. By independently controlling the voltage on the first and second gate electrodes, the threshold voltage of the transistor can be dynamically adjusted to compensate for drift caused by biased voltage stresses during charging and output phases, thereby maintaining stable operation.

Inventive Principle:
Principle #35Parameter changes

2Power

If the pull-up node reaches higher electric potential during output phase, then the output signal level is improved, but the transistor threshold voltage drift increases due to higher bias voltage

Engineering Contradiction:
Improveoutput signal levelVSAvoidthreshold voltage stability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

By applying different voltages to the two gate electrodes, the invention dynamically adjusts the transistor's threshold voltage to compensate for the effects of high bias voltage during the output phase. This parameter change allows the transistor to maintain stable operation even when the pull-up node reaches higher electric potentials, thus improving reliability without sacrificing output signal level.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If the threshold voltage drift reaches a certain degree, then the transistor switching characteristics change, but the display performance deteriorates

Engineering Contradiction:
Improvetransistor switching characteristicsVSAvoiddisplay performance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The dual-gate transistor structure provides a feedback mechanism where the voltage on the second gate electrode can be adjusted in response to threshold voltage drift, thereby compensating for changes in switching characteristics. This feedback approach maintains stable display performance by counteracting the effects of threshold voltage drift before they significantly impact operation.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the stability of the shift register output and enhances display performance by reducing threshold voltage drift and maintaining stable signal output across multiple image frames.

Implementation Method 1

a capacitor C, a clock signal terminal CLK, an input terminal IN, an output terminal, a reset terminal RESET, an inactive signal terminal VSS, and a pull-up node. In a charging phase of the shift register, the input terminal IN inputs a high level signal, the clock signal terminal CLK inputs a low level signal. And, the first transistor M11 is turned on to charge the capacitor C, and an electric potential of the pull-up node PU is increased.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

the first transistor M11 is turned on to charge the capacitor C. The third transistor M13 is turned on, and the signal output terminal OUT of the shift register outputs the low level signal. In an output phase, the input terminal IN inputs the low level signal, and the clock signal terminal inputs the high level signal. And, the third transistor M13 is turned on, the signal output terminal OUT outputs the high level signal.

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10431143B2Shift register, driving method thereof, gate driving circuit and display device
Publication Date: 2019.10.01 BOE TECHNOLOGY GROUP CO LTD
  • US10431143B2 patent drawing
  • US10431143B2 patent drawing
  • US10431143B2 patent drawing

AI summary

A shift register includes a first input circuit, a second input circuit, and a pull-up transistor. The first input circuit is coupled to a first input terminal and a first pull-up node, and configured to electrically connect the first input terminal to the first pull-up node when the first input terminal receives an active signal. The second input circuit is coupled to a second input terminal and a second pull-up node, and configured to electrically connect the second input terminal to the second pull-up node when the second input terminal receives an active signal. The pull-up transistor includes a first gate electrode coupled to the first pull-up node and a second gate electrode coupled to the second pull-up node.