Shift Register Double Pulse Output Narrow Bezel Design

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Solution Overview

Problem

Conventional shift registers in gate driving circuits can only output single pulse signals, failing to meet the requirement for double pulses needed in display panels with external compensation functions, which complicates the design and increases the number of transistors required, making it difficult to achieve a narrow bezel design.

Innovation Solution

A shift register design that includes a display pre-charge reset circuit, sensing cascade circuit, sensing pre-charge reset circuit, pull-down control circuit, and output circuit, allowing for the output of double pulses by sharing circuits and reducing the number of transistors needed, thereby simplifying the gate driving unit and facilitating a narrow bezel design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If two shift registers and a signal combining circuit are used to output double pulses, then the gate driving unit can meet the driving requirements for both display and sensing stages, but the number of TFTs increases significantly, making it difficult to achieve a narrow bezel design

Engineering Contradiction:
Improvedriving capabilityVSAvoidnumber of TFTs
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines two separate shift registers into a single integrated circuit that can output both display drive signals and sensing signals. The circuit uses shared nodes (pull-up node PU and pull-down node PD) and multiplexed control circuits to generate both types of signals from one shift register structure, thereby reducing the total number of TFTs while maintaining dual-stage driving capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shift register circuit is designed to perform multiple functions: it can output display drive signals during the display stage and sensing signals during the sensing stage. The pull-up node and pull-down node are shared between display and sensing operations, and the control circuits are configured to switch between different output modes based on the operational stage, making the circuit universal for both purposes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If a conventional shift register is used, then the device structure is simple, but it can only output single pulse signals and cannot meet the requirements for double pulse output in external compensation functions

Engineering Contradiction:
Improvecircuit structureVSAvoidsignal output capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The shift register incorporates dynamic control mechanisms that allow it to switch between different output modes. Control signals (such as SEN for sensing mode and DIS for display mode) dynamically reconfigure the circuit's behavior, enabling the same circuit to output different types of pulses at different times. This dynamic adaptability allows the circuit to maintain relative simplicity while achieving versatile signal output capabilities.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11568791B2Shift register, gate driving circuit and display device
Publication Date: 2023.01.31 HEFEI BOE ZHUOYIN TECH CO LTD
  • US11568791B2 patent drawing
  • US11568791B2 patent drawing
  • US11568791B2 patent drawing

AI summary

The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.