Shift Register Drive Circuit for Leakage Current Reduction
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Solution Overview
Problem
In active matrix-type liquid crystal display devices, the parasitic capacitance between electrodes in the shift register circuit leads to unnecessary power consumption due to leakage currents, especially when using microcrystalline silicon thin-film transistors, which are more prone to off-leakage compared to amorphous silicon transistors.
Innovation Solution
A scanning signal line drive circuit with a shift register comprising bistable circuits that utilize four-phase clock signals with specific phase shifts and switching elements to manage the charging and discharging of nodes, reducing parasitic capacitance effects and minimizing leakage currents by optimizing the duty ratio and phase relationships of clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microcrystalline silicon thin-film transistors are used in the shift register circuit, then mobility is improved and threshold shift is reduced, but off-leakage current increases leading to higher power consumption
Solution Approach 1:
The patent applies periodic action by using four-phase clock signals (CLK1, CLK2, CLK3, CLK4) that cycle through different states to control the switching elements. This periodic control allows the circuit to maintain proper operation while minimizing leakage current during non-selection periods by systematically transitioning between charged and discharged states of nodes A and B, thereby reducing power consumption while preserving the reliability benefits of microcrystalline silicon TFTs
Solution Approach 2:
The patent changes the operational parameters of the shift register by implementing a specific four-phase clocking scheme with controlled duty ratios and phase relationships. By adjusting the timing and voltage levels of the clock signals, the circuit optimizes the balance between maintaining signal integrity and minimizing leakage current, allowing microcrystalline silicon TFTs to operate with reduced power consumption while maintaining their superior threshold stability
2Reliability
If clock signals are supplied to switching elements to control scanning signal lines, then shift register operation is maintained, but parasitic capacitance causes leakage current and unnecessary power consumption
Solution Approach 1:
The patent applies preliminary action by pre-charging nodes A and B to appropriate voltage levels before the actual scanning operation. The first and second switching elements are controlled to charge these nodes in advance, ensuring that when the scanning signal needs to be transmitted, the circuit is already in the optimal state. This preliminary preparation reduces the need for continuous power supply and minimizes leakage current during non-active periods
Solution Approach 2:
The patent uses periodic action through the four-phase clock signaling scheme that systematically charges and discharges nodes at specific intervals. This periodic control ensures that switching elements are only actively conducting when necessary for signal transmission, while being in high-impedance or discharged states during non-selection periods, thereby maintaining reliable operation while minimizing parasitic capacitance effects and power consumption
Data Source
AI summary
There is realized a scanning signal line drive circuit (in a display device) capable of, even in a case where a circuit in a shift register is formed using a thin-film transistor which is relatively large in off leakage, suppressing unnecessary power consumption due to a leakage current in the thin-film transistor. In at least one embodiment, bistable circuit that forms the shift register includes a thin-film transistor for raising a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin-film transistor, another thin-film transistor for lowering a potential of the region netA, and a region netB connected to a gate terminal of the other thin-film transistor. With this configuration, the potential of the region netB is raised based on a third clock which is advanced in phase by 90 degrees with respect to the first clock and is lowered based on a fourth clock which is delayed in phase by 90 degrees with respect to the first clock.