Cascaded Shift Register Driving Circuit for Display Panel Signal Stability

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Solution Overview

Problem

Existing display panel driving circuits experience unstable output signals, affecting display performance.

Innovation Solution

A display panel with a driving circuit comprising cascaded shift registers, including a first control unit, a second control unit with an adjustment unit, and a third control unit, which maintains a low-level signal of a first node when both the first and third nodes are at low levels, ensuring stability of the output signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional scan driving circuit is used to provide driving signals to pixel circuits, then the display panel can perform scanning and refresh image data in real time, but the output signal becomes unstable, affecting display effects

Engineering Contradiction:
Improveoutput signal stabilityVSAvoiddisplay refresh capability
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The shift register is divided into multiple control units (first control unit, second control unit, third control unit) that operate independently but cooperatively. Each control unit manages specific nodes and signals, allowing the system to maintain signal stability while continuing to perform scanning operations. The segmentation enables precise control over signal transitions without compromising overall display refresh capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit implements feedback mechanisms where control units monitor node states and adjust signals accordingly. The second control unit receives signals from the first control unit and adjusts the second node based on the first node's state, clock signals, and voltage signals. This feedback loop ensures signal stability is maintained while the display continues to refresh image data in real time.

Inventive Principle:
Principle #23Feedback

2Reliability

If the second control unit adjusts the second node based on multiple inputs (first node signal, clock signals, voltage signals), then the output signal stability is improved, but the circuit complexity increases

Engineering Contradiction:
Improveoutput signal stabilityVSAvoidcontrol unit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The second control unit is designed as a multi-functional component that simultaneously processes the first node signal, first clock signal, second clock signal, first voltage signal, and second voltage signal. This universal control unit handles multiple functions (signal conditioning, timing control, voltage regulation) within a single integrated structure, improving output stability without proportionally increasing overall circuit complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Multiple control functions are merged into the second control unit, which combines signal reception, processing, and adjustment capabilities. By merging these functions into a single coordinated unit rather than separate components, the circuit achieves signal stability while minimizing the increase in structural complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11568781B2Display panel and display device
Publication Date: 2023.01.31 XIAMEN TIANMA MICRO ELECTRONICS
  • US11568781B2 patent drawing
  • US11568781B2 patent drawing
  • US11568781B2 patent drawing

AI summary

A display panel and a display device are provided. The display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, where N 2. A shift register of the N levels of shift registers includes: a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal; a second control unit, configured to receive a first voltage signal and a second voltage signal, and control a signal of a second node in response to the signal of the first node, the first clock signal, and a second clock signal; and a third control unit, configured to receive the first voltage signal and the second voltage signal, and control an output signal in response to the signal of the second node and a signal of the third node.