Shift Register Leakage Control via Dual-Gate Segmentation
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Solution Overview
Problem
N-type oxide semiconductor transistors in shift registers experience leakage current at high temperatures, leading to unstable voltage at set nodes and impaired scan pulse generation due to negative threshold voltage shifts.
Innovation Solution
Incorporating a node controller with specific discharging switching devices and clock pulse management within each stage of the shift register, ensuring complete turn-off of transistors during output periods by using clock pulses with higher voltages than the discharging voltage, and optimizing switching device configurations to prevent leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If N-type oxide semiconductor transistors are used in shift register, then the transistor can be turned off at low temperatures, but at high temperatures the threshold voltage shifts negatively causing leakage current and unstable voltage at set node
Solution Approach 1:
The transistor gate is divided into two independent gates (first gate and second gate) that can be controlled separately. This segmentation allows independent optimization of threshold voltage at different temperature conditions, solving the problem of threshold voltage shift at high temperatures while maintaining proper off-state behavior.
Solution Approach 2:
The invention changes the electrical parameters of the transistor by applying different voltages to the two gates. By adjusting the gate voltages dynamically, the threshold voltage can be compensated for temperature variations, preventing leakage current at high temperatures while maintaining stable off-state at low temperatures.
2Reliability
If threshold voltage of oxide semiconductor transistor becomes negative at high temperature, then leakage current increases, but this causes voltage at set node to fall rapidly preventing proper scan pulse generation
Solution Approach 1:
The invention applies preliminary counter-action by using the second gate to preemptively counterbalance the negative threshold voltage shift before it causes significant leakage current. This preliminary adjustment prevents the harmful effect of leakage current and subsequent voltage collapse at the set node.
Solution Approach 2:
By dynamically adjusting the voltage parameters of the two gates based on temperature conditions, the invention changes the transistor's electrical characteristics to maintain stable operation. This parameter adjustment prevents leakage current generation and ensures stable voltage at the set node, enabling reliable scan pulse generation.
Data Source
AI summary
Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.