Shift Register Noise Reduction via Dual-Phase Pull-Down Control
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Solution Overview
Problem
Existing gate driving circuits for liquid crystal displays (LCDs) face challenges in reducing noise at the signal output terminal and ensuring long-term stability, which affects the performance and lifespan of the gate driving circuit, particularly due to the complexity and component count of the Gate Driver on Array (GOA) technology.
Innovation Solution
A shift register design comprising an input circuit, first and second reset circuits, an output circuit, and pull-down control circuits, utilizing a minimal number of transistors to manage voltage signals and clock signals efficiently, thereby reducing noise and enhancing stability. The design includes specific transistor configurations and voltage control mechanisms to achieve stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GOA technology is used to integrate gate driver circuit on array substrate, then material cost and manufacturing process cost are reduced, but noise at signal output terminal increases and long-term stability deteriorates
Solution Approach 1:
The gate driver circuit is divided into multiple independent shift register stages, each with separate control nodes and transistor configurations. This segmentation allows each stage to operate independently with optimized noise control, reducing overall output noise while maintaining the integrated GOA structure on the array substrate
Solution Approach 2:
Different regions of the circuit are assigned different functions: input circuits for signal reception, drive circuits for clock signal generation, output circuits for stable signal delivery, and reset circuits for noise suppression. Each region is optimized locally to achieve overall system reliability while maintaining cost-effective integration
2Reliability
If complex reset control circuits are added to reduce output noise, then output stability is improved, but device complexity increases
Solution Approach 1:
The reset control function is merged with the existing clock signal generation circuitry. The same clock signal that drives the shift register also controls the reset timing, eliminating the need for separate complex reset control circuits while achieving effective noise suppression at the output terminal
Solution Approach 2:
The clock signal serves multiple functions: it drives the shift register operation, controls the timing of signal transmission, and simultaneously manages the reset operation to suppress output noise. This multi-functionality reduces overall circuit complexity while maintaining output stability
Data Source
AI summary
A shift register includes an input circuit, a first reset circuit, an output circuit, a second reset circuit and a first pull-down control circuit. The input circuit may control a voltage of the first node according to a reset signal from a reset signal terminal. The first reset circuit may reset the voltage of the first node according to the reset signal from the reset signal terminal. The output circuit may control an output signal of a signal output terminal according to the voltage of the first node. The second reset circuit may reset the voltage of the first node and the output signal according to a voltage of a second node. The first pull-down control circuit may control the voltage of the second node according to the voltage of the first node based on a first auxiliary voltage signal and a second auxiliary voltage signal, wherein a phase of the first auxiliary voltage signal is opposite to a phase of the second auxiliary voltage signal, and each duty cycles is 50%.