Shift Register Circuit Noise Reduction via Dual Pull-Down Sub-Units

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Solution Overview

Problem

Conventional shift register circuits suffer from high noise-to-signal ratios, which amplify noise when cascaded and can lead to false outputs, especially at high temperatures, due to ineffective noise suppression in the gate driving pulse signals.

Innovation Solution

A shift register circuit design that includes multiple pull-down sub-units with inverted phase signals and duty cycles of 100% to reduce noise levels at the pull-up and output ports, ensuring noise reduction across the entire operation cycle by utilizing both first and second pull-down signals effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional shift register circuits are cascaded to generate gate driving pulse signals, then the integration is achieved on array substrate with cost reduction, but noise levels are amplified and false outputs occur especially at high temperatures

Engineering Contradiction:

Improveintegration costVSAvoidnoise suppression

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The shift register unit is divided into multiple functional sub-units: pull-up sub-unit, first pull-down sub-unit, second pull-down sub-unit, and output sub-unit. Each sub-unit performs a specific function in noise reduction and signal generation, allowing independent optimization of noise suppression without compromising integration benefits

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first pull-down sub-unit is configured to reduce noise at the pull-up node before the output stage, and the second pull-down sub-unit reduces noise at the output port. This preliminary noise suppression prevents noise amplification in cascaded stages, especially under high temperature conditions

Inventive Principle:

Principle #9Preliminary anti-action

2Reliability

If pull-down signals are used to reduce noise at pull-up node and output port, then noise levels are reduced, but the duty cycle allocation between first and second pull-down signals must be precisely controlled to sum to 100%

Engineering Contradiction:

Improvenoise reduction efficiencyVSAvoidduty cycle control

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The first pull-down signal and second pull-down signal operate in complementary periodic cycles, with duty cycles that sum to 100%. This periodic alternating action ensures continuous noise reduction across the entire operation cycle while maintaining simple control logic through natural signal inversion

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The second pull-down signal is inverted in phase relative to the first pull-down signal. This phase inversion automatically creates complementary duty cycles that sum to 100%, simplifying the control mechanism while ensuring optimal noise reduction coverage throughout the operation cycle

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS10140901B2Shift register circuit, display panel and display apparatus having the same

Publication Date: 2018.11.27 BOE TECHNOLOGY GROUP CO LTD

AI summary

The present application discloses a shift register circuit having a pull-down drive sub-unit providing a first pull-down signal to a pull-down node; a first pull-down sub-unit connected to the pull-down node, a pull-up node, and an output port, the first pull-down sub-unit being configured to reduce noise level at the pull-up node and/or the output port based on the first pull-down signal; and at least one second pull-down sub-unit, each of the at least one second pull-down sub-unit having a pull-down input port, each of the at least one second pull-down sub-unit connected to the pull-up node and the output port, and being configured to reduce noise level at the pull-up node and/or output port based on the second pull-down signal inputted into the pull-down input port.