Shift Register Unit with Dual Pulling-Down Structure for Leakage Prevention
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Solution Overview
Problem
The existing shift register circuits using oxide TFTs, which are depletion transistors, suffer from leakage current issues due to the inability to turn off the transistors, unlike enhancement transistors used in a-si and p-si techniques, leading to circuit malfunction.
Innovation Solution
A shift register unit design that includes a driving transistor with a dual pulling-down structure and insulation pulling-up module, utilizing two different pulling-down levels to ensure the transistor is turned off, thereby preventing leakage current, comprising a driving transistor, a first capacitor, an output pulling-up module, a carry signal output terminal, an output pulling-down module, a first pulling-down module, and an insulation pulling-up module.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If oxide TFTs (depletion transistors) are used in the shift register circuit, then lower cost and higher mobility are achieved, but leakage current increases due to inability to turn off the transistors
Solution Approach 1:
The patent introduces a level shift transistor as an intermediary component between the depletion TFT and the circuit logic. This level shift transistor acts as a mediator that converts the output signal from the depletion TFT, enabling proper logic level translation and signal conditioning while allowing the depletion TFT to operate in its native depletion mode without requiring complete turn-off capability
Solution Approach 2:
The patent changes the operating parameters of the depletion TFT by adjusting the threshold voltage through back-gate control or doping modifications. By optimizing the threshold voltage parameter, the depletion TFT can maintain low leakage current while preserving high mobility characteristics, resolving the contradiction between these two parameters
2Device complexity
If traditional basic shift register unit is used with depletion TFTs, then circuit simplicity is maintained, but circuit malfunction occurs due to leakage current
Solution Approach 1:
The patent segments the shift register unit into distinct functional modules: the depletion TFT stage, the level shift transistor stage, and the output stage. This segmentation allows each module to be optimized independently - the depletion TFT for high mobility, the level shift transistor for proper logic level translation, and the output stage for drive capability - while maintaining overall circuit reliability
Solution Approach 2:
The level shift transistor serves as an intermediary that bridges the depletion TFT and the subsequent circuit stages. It translates the analog-like output of the depletion TFT into clean digital logic levels, preventing leakage current from affecting downstream circuits while maintaining the simplicity of the overall architecture
Data Source
AI summary
A shift register unit, a shift register and a display apparatus, insulate a start charging capacitor from the gate of the driving transistor, and adopt a dual pulling-down structure for the gate of the driving transistor and the output terminal simultaneously thereby the transistor can be turned off normally and a leakage is prevented. The shift register unit comprises: a driving transistor (T1); a first capacitor (C1) for storing an electrical signal from a previous stage; an output pulling-up module (400) connected with a drain of the driving transistor (T1); a drive output terminal (OUT (N)) connected with a source of the driving transistor (T1); a carry signal output terminal connected with a gate of the driving transistor (T1) or the drive output terminal (OUT (N)); an output pulling-down module (100) connected with a source of the driving transistor (T1); a first pulling-down module (200), which is connected with the gate of the driving transistor (T1) through a pulling-up node (PU) and connected with the output pulling-down module (100) through a pulling-down node (PD); and an insulation pulling-up module (300) connected between the pulling-up node (PU) and the first capacitor (C1).