Shift Register Leakage Current Control via Dual-Voltage Pull-Down

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Solution Overview

Problem

Conventional shift registers in liquid crystal display gate driving devices experience significant leakage current at high temperatures due to the transfer characteristic curve, leading to unstable signal output and abnormal display issues.

Innovation Solution

The proposed shift register design includes an inputting circuit, pulling down driving circuit, resetting circuit, first outputting circuit, controlling circuit, and second outputting circuit, which control node potentials to achieve a cut-off negative voltage twice that of the low-level signal terminal, improving stability without an external reference voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional shift register uses a cut-off voltage of -8V for the gate of the thin film transistor in the outputting circuit, then the switch transistor is turned off perfectly at normal temperatures, but leakage current becomes large at high temperatures causing signal fluctuation and abnormal display

Engineering Contradiction:
Improvesignal output stabilityVSAvoidleakage current
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the cut-off voltage parameter from -8V to -16V (twice the low level signal terminal voltage) to compensate for temperature-induced leakage current. This parameter adjustment ensures the switch transistor remains fully off at high temperatures, eliminating signal fluctuation and abnormal display while maintaining perfect turn-off at normal temperatures.

Inventive Principle:
Principle #35Parameter changes

2Ease of operation

If the Output terminal is pulled down to -8V by the low level signal terminal (Vss), then the voltage difference (Vgs) between gate and source is 0V, but this causes large leakage current at high temperatures

Engineering Contradiction:
Improvecircuit simplicityVSAvoidsignal output stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent modifies the voltage parameter from -8V to -16V by connecting the first terminal of the second outputting circuit to twice the low level signal terminal voltage through the controlling circuit. This maintains the simple circuit structure while dramatically improving signal output stability by eliminating temperature-dependent leakage current.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If the transfer characteristic curve is not adjusted, then the production process remains simple, but the switch transistor cannot be fully turned off at high temperatures

Engineering Contradiction:
Improveproduction process simplicityVSAvoidswitch transistor turn-off performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Instead of modifying the transfer characteristic curve through complex production processes, the patent changes the operating voltage parameter to -16V. This approach maintains simple production processes while achieving complete switch transistor turn-off at high temperatures, solving the reliability issue without complicating manufacturing.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10140910B2Shift register, a gate line driving circuit, an array substrate and a display apparatus
Publication Date: 2018.11.27 BOE TECHNOLOGY GROUP CO LTD
  • US10140910B2 patent drawing
  • US10140910B2 patent drawing
  • US10140910B2 patent drawing

AI summary

The present disclosure provides a shift register, a gate line driving circuit, an array substrate and a display apparatus. The shift register comprises: an inputting circuit for controlling a potential of a pulling up node (PU); a pulling down driving circuit for controlling the potentials of the PU and a pulling down node to be different; a resetting circuit for pulling down the PU and a signal outputting terminal (Output); a first outputting circuit for pulling down the Output; a second outputting terminal for outputting a signal from a clock signal terminal via the Output; a controlling circuit for connecting the second outputting circuit with the PU when the PU is at a high level and pulling the first terminal of the second outputting circuit down to a potential as twice as the potential of the low level signal terminal when the PU is at a low level.