Shift Register Soft-Error Protection via ECC Feedback
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Solution Overview
Problem
Existing error-correcting code (ECC) circuitry in shift registers can only correct a single error and fails to address subsequent soft-errors, leading to data corruption and the need for system reboot.
Innovation Solution
A circuit and method that compares output data from a shift register with ECC output, identifies correctable errors, and replaces erroneous bits with corrected values from the ECC, allowing continuous error correction without system interruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard ECC logic is used to correct errors in the shift register, then single errors can be corrected, but additional soft-errors cannot be corrected and require system reboot
Solution Approach 1:
The patent implements a feedback mechanism where the ECC circuit's output is fed back to the shift register input through a selector. When an error is detected and corrected by the ECC logic, the corrected value is fed back to overwrite the erroneous value in the shift register, enabling continuous correction of multiple errors without system reboot.
Solution Approach 2:
The patent combines the shift register and ECC circuit into an integrated error correction system. The ECC logic is coupled directly to the shift register output, and the corrected values are merged back into the shift register through the selector, creating a unified system that continuously corrects errors.
2Device complexity
If the ECC logic corrects only a single error, then the circuit complexity remains low, but any additional soft-errors are not corrected
Solution Approach 1:
The patent enables continuous error correction by creating a closed-loop system where the ECC logic continuously monitors the shift register output and feeds corrected values back when errors are detected. This continuous action allows multiple errors to be corrected sequentially without interrupting system operation.
Solution Approach 2:
The ECC logic performs preliminary error detection and correction before the erroneous data can cause system failure. By continuously monitoring and correcting errors as they occur in the shift register, the system prevents data corruption before it propagates.
3Reliability
If multiple errors occur in the shift register, then data corruption occurs requiring system reboot, but the ECC logic cannot handle these additional errors
Solution Approach 1:
The feedback loop continuously monitors the shift register and ECC output, detecting errors and immediately feeding corrected values back to prevent data corruption. This real-time feedback eliminates the need for system reboots even when multiple errors occur.
Solution Approach 2:
The system prepares for potential errors by having the ECC logic ready to detect and correct them before they can cause data corruption. The feedback mechanism ensures corrected values are immediately available to prevent future errors from propagating.
Data Source
AI summary
Embodiments of the present disclosure provide an a circuit including: first logic to compare output data from the shift register with output data from error correcting code circuitry (ECC), to output an error signal in response to a data bit output from the shift register being different from a data bit output from the ECC; second logic for receiving the error signal from the first logic gate, and a correctability signal from the ECC, to output an overwrite signal in response to receiving the error signal and the correctability signal; and a selector receiving the overwrite signal and the data bit of the output data from the ECC, and coupled between a data source and an input line to the shift register. The selector causes the shift register to receive the ECC output in response to receiving the overwrite signal.