Shift Register Gate Drive for Partial-Refresh Edge Stability
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Solution Overview
Problem
Display panels face issues with power consumption due to increased refresh rates, particularly in partial-refresh scenarios, where drive output signals cross transition edges of enable signals, leading to abnormal pixel operations.
Innovation Solution
A shift register unit with a sampling circuit and control circuit is introduced, allowing selective refresh of partial regions at high rates while maintaining normal operation by ensuring correct signal output during changes in enable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the refresh rate of the display panel is increased to improve display quality and responsiveness, then the display performance is improved, but the power consumption increases
Solution Approach 1:
The display panel is divided into multiple regions with different refresh rates. The gate drive circuit is segmented into multiple shift register units that can independently control different regions, allowing partial-refresh operations where only specific regions are refreshed at high rates while other regions use lower refresh rates, thereby reducing overall power consumption.
Solution Approach 2:
The refresh rate of different regions is made dynamic and adjustable based on content requirements. The control circuit dynamically selects whether to output a gate scan signal or gate off signal, enabling the display to adaptively change refresh rates in different regions and at different times, optimizing power consumption while maintaining display quality where needed.
2Reliability
If the gate drive circuit outputs signals during transition edges of enable signals to maintain signal integrity, then the signal accuracy is improved, but abnormal pixel operations occur
Solution Approach 1:
The sampling circuit performs preliminary sampling of the enable signal before the main signal processing. By sampling the enable signal at the appropriate timing (controlled by sampling control signals), the circuit prepares the correct signal state in advance, preventing abnormal pixel operations that would occur if signals were output during transition edges.
Solution Approach 2:
The sampling circuit acts as an intermediary between the enable signal and the main signal processing path. It uses sampling control signals to mediate the timing relationship, ensuring that signal output occurs at stable periods rather than during transition edges, thus maintaining both signal accuracy and pixel operation stability.
3Measurement precision
If a sampling circuit is added to control signal timing, then signal output accuracy is improved, but the device complexity increases
Solution Approach 1:
The sampling circuit is designed to perform multiple functions: it samples the enable signal, generates timing control signals, and coordinates with the shift register units. By making the sampling circuit multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity while achieving precise signal output timing.
Data Source
AI summary
A shift register unit, a gate drive circuit, a display panel, and a driving method. An example shift register unit includes: a first shift register, which is configured to output a cascade signal by a cascade output end; a sampling circuit, which is coupled to a first node and is configured to provide a signal at an enabling end to the first node in response to a signal at a sampling control end; and a control circuit, which is coupled to the cascade output end and the first node, and is configured to output, in response to a signal of the first node, a gate scanning signal having the same time sequence as the cascade signal by a driving output end, or to output a gate cut-off signal by the driving output end.