Shift Register With Enable Modules For Display Uniformity
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Solution Overview
Problem
Large display panels face issues with display brightness uniformity due to increased pixel load on scanning signal lines, leading to delays and differences in brightness between pixels close to and far from the shift register.
Innovation Solution
The implementation of a shift register with multiple cascaded units, each including a shift module and enable modules, which generate and transmit gate driving signals to reduce load and delay, ensuring uniformity across pixels in a row.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of pixels electrically connected to a same scanning signal line increases, then the display panel can support larger size and more pixels, but the load on the scanning signal line increases causing large delay and brightness difference between pixels
Solution Approach 1:
The patent divides the display panel into multiple sub-panels, with each sub-panel containing a subset of pixels and its own dedicated scanning signal line. This segmentation reduces the number of pixels per scanning signal line from the full panel count to a manageable subset, thereby reducing signal transmission delay while maintaining the ability to display large numbers of pixels overall through the coordinated operation of multiple sub-panels.
2Quantity of substance
If the number of pixels electrically connected to a same scanning signal line increases, then the display panel can support larger size and more pixels, but the load on the scanning signal line increases causing brightness difference between pixels close to and far from the shift register
Solution Approach 1:
By segmenting the display into multiple sub-panels with dedicated scanning signal lines, each sub-panel experiences reduced signal transmission distance and lower load, resulting in more uniform brightness across all pixels in that sub-panel. The overall display achieves brightness uniformity through the combined effect of multiple uniformly performing sub-panels.
Solution Approach 2:
Each sub-panel is configured with its own scanning signal line dedicated to serving only the pixels within that sub-panel. This local quality approach ensures that each region of the display receives optimized signal delivery tailored to its specific pixel count and distance from the shift register, eliminating the brightness gradients that would occur in a single large-panel configuration.
3Device complexity
If a single shift register unit drives more pixels, then the shift register structure is simpler, but the gate driving signal experiences large delay and cannot maintain uniform display
Solution Approach 1:
The patent assigns dedicated scanning signal lines to specific pixel groups, effectively segmenting the driving responsibility. Each scanning signal line serves a localized pixel subset, reducing the number of pixels that any single signal path must drive and thereby minimizing transmission delay while maintaining structural simplicity in the shift register architecture.
Solution Approach 2:
The scanning signal line acts as an intermediary between the shift register and the pixel groups. By introducing this intermediate signal delivery mechanism dedicated to specific pixel subsets, the system reduces the direct load on the shift register output, thereby reducing delay without requiring the shift register itself to become more complex.
4Area of stationary object
If the scanning signal line transmits gate driving signal to more pixels, then the display panel covers larger area, but the signal experiences large delay resulting in brightness difference
Solution Approach 1:
The display panel is segmented into multiple sub-panels, each with its own dedicated scanning signal line. This allows the overall display to cover a large area through the combination of multiple sub-panels while each individual signal line maintains short transmission distance to its served pixels, preventing signal delay from scaling with the total display area.
Data Source
AI summary
A shift register includes n shift register units which are cascaded. Each shift register unit includes a shift module and multiple enable modules. The shift module of an i-th-level shift register unit is configured to receive and latch a shift signal output by the shift module in an (i−1)-th-level shift register unit. The multiple enable modules of the i-th-level shift register unit are electrically connected to the shift module of the i-th-level shift register unit, and each of the multiple enable modules is configured to generate a gate driving signal according to the shift signal. n and i are positive integers, 1≤i≤n.