Shift Register Gate Layout to Prevent Antenna-Effect ESD

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Solution Overview

Problem

As semiconductor display devices increase in size, the larger transistors required for driver circuits lead to increased wiring areas, which are prone to electrostatic destruction due to the 'antenna effect' during manufacturing, reducing yield and reliability.

Innovation Solution

Dividing conductive films functioning as gate electrodes into multiple layers and electrically connecting them with a different conductive film to reduce the area of each gate electrode, thereby minimizing charge accumulation and electrostatic damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If the transistor size is increased to meet current supply ability requirements for larger panels, then the current supply ability is improved, but the area of the gate electrode wiring is increased, leading to charge accumulation and electrostatic destruction

Engineering Contradiction:
Improvecurrent supply abilityVSAvoidelectrostatic destruction probability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The gate electrode wiring is divided into multiple separate conductive films (first conductive film and second conductive film) instead of using a single continuous wiring. This segmentation reduces the total area of each individual conductive film, thereby reducing charge accumulation from the antenna effect while still providing the necessary current supply ability through parallel paths

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a third layer (different from the layers containing the first and second conductive films) to electrically connect the divided conductive films. This dimensional approach allows the gate electrode to be split into multiple smaller areas in the plan view while maintaining electrical continuity through vertical connections in the third dimension

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If a single conductive film is used as the gate electrode, then the layout is simpler, but the area of the conductive film is large, causing charge accumulation and reducing yield

Engineering Contradiction:
Improvelayout complexityVSAvoidyield
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The single continuous gate electrode conductive film is segmented into multiple separate conductive films (first and second conductive films). This reduces the area of each individual film, minimizing charge accumulation and electrostatic destruction risk, while the films are electrically connected through a third-layer conductive film to maintain functionality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A conductive film in a third layer acts as an intermediary to electrically connect the first and second conductive films. This intermediary structure allows the gate electrode to be divided into smaller segments while maintaining electrical continuity, thus reducing antenna effect without compromising device operation

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240363181A1Semiconductor device
Publication Date: 2024.10.31 SEMICON ENERGY LAB CO LTD
  • US20240363181A1 patent drawing
  • US20240363181A1 patent drawing
  • US20240363181A1 patent drawing

AI summary

A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.